Merge pull request #2255 from whitequark/bison-Werror-conflicts

verilog_parser: turn S/R and R/R conflicts into hard errors

frontends/verilog/Makefile.inc

@@ -6,7 +6,7 @@ GENFILES += frontends/verilog/verilog_lexer.cc
 
 frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
 	$(Q) mkdir -p $(dir $@)
-	$(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<
+	$(P) $(BISON) -Werror=conflicts-sr,error=conflicts-rr -o $@ -d -r all -b frontends/verilog/verilog_parser $<
 
 frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
 

frontends/verilog/verilog_parser.y

@@ -747,7 +747,7 @@ module_body:
 module_body_stmt:
 	task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
 	enum_decl | struct_decl |
-	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';';
+	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
 
 checker_decl:
 	TOK_CHECKER TOK_ID ';' {
@@ -1331,45 +1331,36 @@ ignspec_id:
 param_signed:
 	TOK_SIGNED {
 		astbuf1->is_signed = true;
-	} | TOK_UNSIGNED {
-		astbuf1->is_signed = false;
 	} | /* empty */;
 
 param_integer:
 	TOK_INTEGER {
+		if (astbuf1->children.size() != 1)
+			frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
 		astbuf1->children.push_back(new AstNode(AST_RANGE));
 		astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
 		astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
 		astbuf1->is_signed = true;
-	}
+	} | /* empty */;
 
 param_real:
 	TOK_REAL {
+		if (astbuf1->children.size() != 1)
+			frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
 		astbuf1->children.push_back(new AstNode(AST_REALVALUE));
-	}
-
-param_logic:
-	TOK_LOGIC {
-		// SV LRM 6.11, Table 6-8: logic -- 4-state, user-defined vector size, unsigned
-		astbuf1->is_signed = false;
-		astbuf1->is_logic = true;
-	}
+	} | /* empty */;
 
 param_range:
 	range {
 		if ($1 != NULL) {
+			if (astbuf1->children.size() != 1)
+				frontend_verilog_yyerror("integer/real parameters should not have a range.");
 			astbuf1->children.push_back($1);
 		}
 	};
 
-param_integer_type: param_integer param_signed
-param_range_type: type_vec param_signed param_range
-param_implicit_type: param_signed param_range
-
-param_integer_vector_type: param_logic param_signed param_range
-
 param_type:
-	param_integer_type | param_integer_vector_type | param_real | param_range_type | param_implicit_type |
+	param_signed param_integer param_real param_range |
 	hierarchical_type_id {
 		astbuf1->is_custom_type = true;
 		astbuf1->children.push_back(new AstNode(AST_WIRETYPE));

tests/various/integer_range_bad_syntax.ys

@@ -1,6 +0,0 @@
-logger -expect error "syntax error, unexpected" 1
-read_verilog -sv <<EOT
-module test_integer_range();
-parameter integer [31:0] a = 0;
-endmodule
-EOT

tests/various/integer_real_bad_syntax.ys

@@ -1,6 +0,0 @@
-logger -expect error "syntax error, unexpected TOK_REAL" 1
-read_verilog -sv <<EOT
-module test_integer_real();
-parameter integer real a = 0;
-endmodule
-EOT

tests/various/logic_param_simple.ys

@@ -1,9 +0,0 @@
-read_verilog -sv <<EOT
-module test_logic_param();
-parameter logic                 a = 0;
-parameter logic [31:0]          e = 0;
-parameter logic signed          b = 0;
-parameter logic unsigned        c = 0;
-parameter logic unsigned [31:0] d = 0;
-endmodule
-EOT

tests/various/signed.ys

@@ -1,28 +0,0 @@
-# SV LRM A2.2.1
-
-read_verilog -sv <<EOT
-module test_signed();
-parameter integer signed  a = 0;
-parameter integer unsigned  b = 0;
-
-endmodule
-EOT
-
-design -reset
-read_verilog -sv <<EOT
-module test_signed();
-parameter logic signed [7:0] a = 0;
-parameter logic unsigned [7:0] b = 0;
-
-endmodule
-EOT
-
-design -reset
-logger -expect error "syntax error, unexpected TOK_INTEGER" 1
-read_verilog -sv <<EOT
-module test_signed();
-parameter signed integer a = 0;
-parameter unsigned integer b = 0;
-
-endmodule
-EOT