mirror of https://github.com/YosysHQ/yosys.git
Add fileinfo to firrtl backend for assignments and non-instance cells
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3e04e29dec
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@ -512,11 +512,12 @@ struct FirrtlWorker
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string primop;
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bool always_uint = false;
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string y_id = make_id(cell->name);
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std::string cellFileinfo = getFileinfo(cell->attributes);
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if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
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{
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string a_expr = make_expr(cell->getPort("\\A"));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
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if (a_signed) {
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a_expr = "asSInt(" + a_expr + ")";
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@ -556,7 +557,7 @@ struct FirrtlWorker
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if ((firrtl_is_signed && !always_uint))
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expr = stringf("asUInt(%s)", expr.c_str());
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Y"));
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continue;
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@ -567,7 +568,8 @@ struct FirrtlWorker
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{
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string a_expr = make_expr(cell->getPort("\\A"));
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string b_expr = make_expr(cell->getPort("\\B"));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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std::string cellFileinfo = getFileinfo(cell->attributes);
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wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
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if (a_signed) {
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a_expr = "asSInt(" + a_expr + ")";
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@ -783,7 +785,7 @@ struct FirrtlWorker
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if ((firrtl_is_signed && !always_uint))
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expr = stringf("asUInt(%s)", expr.c_str());
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Y"));
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continue;
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@ -795,11 +797,11 @@ struct FirrtlWorker
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string a_expr = make_expr(cell->getPort("\\A"));
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string b_expr = make_expr(cell->getPort("\\B"));
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string s_expr = make_expr(cell->getPort("\\S"));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), width));
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wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), width, cellFileinfo.c_str()));
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string expr = stringf("mux(%s, %s, %s)", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Y"));
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continue;
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@ -938,9 +940,9 @@ struct FirrtlWorker
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string expr = make_expr(cell->getPort("\\D"));
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string clk_expr = "asClock(" + make_expr(cell->getPort("\\CLK")) + ")";
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wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s\n", y_id.c_str(), width, clk_expr.c_str()));
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wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s %s\n", y_id.c_str(), width, clk_expr.c_str(), cellFileinfo.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
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cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
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register_reverse_wire_map(y_id, cell->getPort("\\Q"));
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continue;
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@ -1030,6 +1032,7 @@ struct FirrtlWorker
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for (auto wire : module->wires())
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{
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string expr;
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std::string wireFileinfo = getFileinfo(wire->attributes);
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if (wire->port_input)
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continue;
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@ -1088,14 +1091,20 @@ struct FirrtlWorker
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if (is_valid) {
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if (make_unconn_id) {
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wire_decls.push_back(stringf(" wire %s: UInt<1>\n", unconn_id.c_str()));
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wire_decls.push_back(stringf(" wire %s: UInt<1> %s\n", unconn_id.c_str(), wireFileinfo.c_str()));
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// `invalid` is a firrtl construction for simulation so we will not
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// tag it with a @[fileinfo] tag as it doesn't directly correspond to
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// a specific line of verilog code.
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wire_decls.push_back(stringf(" %s is invalid\n", unconn_id.c_str()));
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}
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wire_exprs.push_back(stringf(" %s <= %s\n", make_id(wire->name), expr.c_str()));
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wire_exprs.push_back(stringf(" %s <= %s %s\n", make_id(wire->name), expr.c_str(), wireFileinfo.c_str()));
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} else {
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if (make_unconn_id) {
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unconn_id.clear();
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}
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// `invalid` is a firrtl construction for simulation so we will not
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// tag it with a @[fileinfo] tag as it doesn't directly correspond to
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// a specific line of verilog code.
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wire_decls.push_back(stringf(" %s is invalid\n", make_id(wire->name)));
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}
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}
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