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Added support for "assign" statements in abc vlparse

This commit is contained in:
Clifford Wolf 2013-06-15 13:50:38 +02:00
parent 6ef8c6fb8a
commit c09b66b2a1
2 changed files with 39 additions and 2 deletions
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8
passes/abc/abc.cc
View File

@ -572,6 +572,14 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
} }
} }
for (auto conn : mapped_mod->connections) {
if (!conn.first.is_fully_const())
conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks[0].wire->name)]);
if (!conn.second.is_fully_const())
conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]);
module->connections.push_back(conn);
}
for (auto &it : cell_stats) for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second); log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
int in_wires = 0, out_wires = 0; int in_wires = 0, out_wires = 0;

33
passes/abc/vlparse.cc
View File

@ -53,12 +53,12 @@ static int lex(FILE *f)
return token(lex_tok); return token(lex_tok);
if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') || if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') ||
('0' <= ch && ch <= '9') || ch == '_') { ('0' <= ch && ch <= '9') || ch == '_' || ch == '\'') {
lex_str = char(ch); lex_str = char(ch);
while (1) { while (1) {
ch = getc(f); ch = getc(f);
if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') || if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') ||
('0' <= ch && ch <= '9') || ch == '_') { ('0' <= ch && ch <= '9') || ch == '_' || ch == '\'') {
lex_str += char(ch); lex_str += char(ch);
continue; continue;
} }
@ -143,6 +143,35 @@ RTLIL::Design *abc_parse_verilog(FILE *f)
} }
} }
} }
else if (lex_str == "assign")
{
std::string lhs, rhs;
if (lex(f) != 256)
goto error;
lhs = lex_str;
if (lex(f) != '=')
goto error;
if (lex(f) != 256)
goto error;
rhs = lex_str;
if (lex(f) != ';')
goto error;
if (module->wires.count(RTLIL::escape_id(lhs)) == 0)
goto error;
if (rhs == "1'b0")
module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), RTLIL::SigSpec(0, 1)));
else if (rhs == "1'b1")
module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), RTLIL::SigSpec(1, 1)));
else if (module->wires.count(RTLIL::escape_id(rhs)) > 0)
module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), module->wires.at(RTLIL::escape_id(rhs))));
else
goto error;
}
else else
{ {
std::string cell_type = lex_str; std::string cell_type = lex_str;