mirror of https://github.com/YosysHQ/yosys.git
Give initial wire unique ID, fixes #2914
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07dde32bf1
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@ -44,6 +44,7 @@ std::string auto_prefix, extmem_prefix;
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RTLIL::Module *active_module;
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RTLIL::Module *active_module;
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dict<RTLIL::SigBit, RTLIL::State> active_initdata;
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dict<RTLIL::SigBit, RTLIL::State> active_initdata;
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SigMap active_sigmap;
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SigMap active_sigmap;
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IdString initial_id;
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void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
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void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
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{
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{
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@ -1943,7 +1944,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
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f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*");
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f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*");
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if (!systemverilog)
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if (!systemverilog)
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f << indent + " " << "if (" << id("\\initial") << ") begin end\n";
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f << indent + " " << "if (" << id(initial_id) << ") begin end\n";
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dump_case_body(f, indent, &proc->root_case, true);
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dump_case_body(f, indent, &proc->root_case, true);
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std::string backup_indent = indent;
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std::string backup_indent = indent;
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@ -2077,9 +2078,10 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
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}
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}
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}
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}
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f << stringf(");\n");
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f << stringf(");\n");
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if (!systemverilog && !module->processes.empty()) {
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if (!systemverilog && !module->processes.empty())
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initial_id = NEW_ID;
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f << indent + " " << "reg " << id("\\initial") << " = 0;\n";
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f << indent + " " << "reg " << id(initial_id) << " = 0;\n";
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}
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for (auto w : module->wires())
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for (auto w : module->wires())
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dump_wire(f, indent + " ", w);
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dump_wire(f, indent + " ", w);
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