mirror of https://github.com/YosysHQ/yosys.git
Reimplement opt_share to work on $alu and $pmux
This commit is contained in:
Bogdan Vukobratovic
parent
07c4a7d438
commit
c075486c59
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@ -31,12 +31,21 @@ PRIVATE_NAMESPACE_BEGIN
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SigMap assign_map;
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struct InPort {
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RTLIL::SigSpec sig;
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RTLIL::Cell *pmux;
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int port_id;
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RTLIL::Cell *alu;
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InPort(RTLIL::SigSpec s, RTLIL::Cell *c, int p, RTLIL::Cell *a = NULL) : sig(s), pmux(c), port_id(p), alu(a) {}
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};
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// Helper class that to track whether a SigSpec is signed and whether it is
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// connected to the \\B port of the $sub cell, which makes its sign prefix
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// negative.
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struct ExtSigSpec {
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RTLIL::SigSpec sig;
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bool sign;
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RTLIL::SigSpec sign;
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bool is_signed;
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ExtSigSpec() {}
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@ -45,7 +54,7 @@ struct ExtSigSpec {
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ExtSigSpec(RTLIL::Cell *cell, RTLIL::IdString port_name, SigMap *sigmap)
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{
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sign = (cell->type == "$sub") && (port_name == "\\B");
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sign = (port_name == "\\B") ? cell->getPort("\\BI") : RTLIL::Const(0, 1);
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sig = (*sigmap)(cell->getPort(port_name));
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is_signed = false;
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@ -67,23 +76,22 @@ struct ExtSigSpec {
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return is_signed < other.is_signed;
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}
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bool operator==(const RTLIL::SigSpec &other) const { return sign ? false : sig == other; }
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bool operator==(const RTLIL::SigSpec &other) const { return (sign != RTLIL::Const(0, 1)) ? false : sig == other; }
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bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig; }
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};
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void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<RTLIL::Cell *> &operators, int offset, int width,
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void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<InPort> &ports, int offset, int width,
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const ExtSigSpec &operand)
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{
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std::vector<ExtSigSpec> muxed_operands;
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int max_width = 0;
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for (auto op : operators) {
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for (auto &conn : op->connections()) {
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if (op->output(conn.first))
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continue;
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for (const auto& p : ports) {
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auto op = p.alu;
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if (conn.second != operand.sig) {
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auto operand = ExtSigSpec(op, conn.first, &assign_map);
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for (RTLIL::IdString port_name : {"\\A", "\\B"}) {
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if (op->getPort(port_name) != operand.sig) {
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auto operand = ExtSigSpec(op, port_name, &assign_map);
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if (operand.sig.size() > max_width) {
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max_width = operand.sig.size();
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}
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@ -97,30 +105,61 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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operand.sig.extend_u0(max_width, operand.is_signed);
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}
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auto shared_op = operators[0];
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auto shared_op = ports[0].alu;
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for (auto op : operators) {
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for (const auto& p : ports) {
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auto op = p.alu;
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if (op == shared_op)
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continue;
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module->remove(op);
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}
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RTLIL::SigSpec mux_out = mux->getPort("\\Y");
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if (muxed_operands[0].sign != muxed_operands[1].sign) {
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muxed_operands[1] = ExtSigSpec(module->Neg(NEW_ID, muxed_operands[1].sig, muxed_operands[1].is_signed));
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for (auto &muxed_op : muxed_operands) {
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if (muxed_op.sign != muxed_operands[0].sign) {
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muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed));
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}
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}
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auto mux_to_oper = module->Mux(NEW_ID, muxed_operands[0].sig, muxed_operands[1].sig, mux->getPort("\\S"));
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RTLIL::SigSpec mux_y = mux->getPort("\\Y");
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RTLIL::SigSpec mux_a = mux->getPort("\\A");
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RTLIL::SigSpec mux_b = mux->getPort("\\B");
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RTLIL::SigSpec mux_s = mux->getPort("\\S");
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shared_op->setPort("\\Y", mux_out.extract(offset, width));
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RTLIL::SigSpec alu_x = shared_op->getPort("\\X");
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RTLIL::SigSpec alu_co = shared_op->getPort("\\CO");
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RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
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RTLIL::SigSpec shared_pmux_b;
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RTLIL::SigSpec shared_pmux_s;
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shared_op->setPort("\\Y", shared_op->getPort("\\Y").extract(0, width));
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if (mux->type == "$pmux") {
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shared_pmux_s = RTLIL::SigSpec();
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for (const auto&p: ports) {
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shared_pmux_s.append(mux_s[p.port_id]);
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mux_b.replace(p.port_id * mux_a.size() + offset, shared_op->getPort("\\Y"));
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}
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} else {
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shared_pmux_s = RTLIL::SigSpec{mux_s, module->Not(NEW_ID, mux_s)};
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mux_a.replace(offset, shared_op->getPort("\\Y"));
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mux_b.replace(offset, shared_op->getPort("\\Y"));
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}
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mux->setPort("\\Y", mux_y);
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mux->setPort("\\S", mux_s);
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mux->setPort("\\B", mux_b);
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for (const auto &op : muxed_operands)
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shared_pmux_b.append(op.sig);
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auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
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shared_op->setPort("\\X", alu_x.extract(0, width));
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shared_op->setPort("\\CO", alu_co.extract(0, width));
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shared_op->setParam("\\Y_WIDTH", width);
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auto dummy = module->addWire(NEW_ID, width);
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mux_out.replace(offset, dummy);
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mux->setPort("\\Y", mux_out);
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if (shared_op->getPort("\\A") == operand.sig) {
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shared_op->setPort("\\B", mux_to_oper);
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shared_op->setParam("\\B_WIDTH", max_width);
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@ -128,81 +167,132 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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shared_op->setPort("\\A", mux_to_oper);
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shared_op->setParam("\\A_WIDTH", max_width);
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}
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}
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typedef struct {
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RTLIL::Cell *mux;
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std::vector<RTLIL::Cell *> operators;
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std::vector<InPort> ports;
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int offset;
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int width;
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ExtSigSpec shared_operand;
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} shared_op_t;
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bool find_op_res_width(int offset, int &width, RTLIL::SigSpec porta, RTLIL::SigSpec portb,
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const dict<RTLIL::SigBit, RTLIL::SigSpec> &op_outbit_to_outsig, const dict<RTLIL::SigBit, int> &op_outbit_user_cnt)
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template <typename T> void remove_val(std::vector<T> &v, const std::vector<T> &vals)
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{
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auto val_iter = vals.rbegin();
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for (auto i = v.rbegin(); i != v.rend(); ++i)
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if ((val_iter != vals.rend()) && (*i == *val_iter)) {
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v.erase(i.base() - 1);
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++val_iter;
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}
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}
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bool find_op_res_width(int offset, int &width, std::vector<InPort*>& ports, const dict<RTLIL::SigBit, RTLIL::SigSpec> &op_outbit_to_outsig)
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{
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std::array<RTLIL::SigSpec, 2> op_outsigs{op_outbit_to_outsig.at(porta[offset]), op_outbit_to_outsig.at(portb[offset])};
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std::vector<RTLIL::SigSpec> op_outsigs;
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dict<int, std::set<InPort*>> op_outsig_span;
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std::transform(ports.begin(), ports.end(), std::back_inserter(op_outsigs), [&](InPort *p) { return op_outbit_to_outsig.at(p->sig[offset]); });
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std::vector<bool> finished(ports.size(), false);
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width = 0;
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bool multi_user = false;
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while (true) {
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for (const auto &op_outsig : op_outsigs)
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if (op_outbit_user_cnt.at(op_outsig[width]) > 1)
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multi_user = true;
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std::function<bool()> all_finished = [&] { return std::find(std::begin(finished), std::end(finished), false) == end(finished);};
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while (!all_finished())
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{
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++offset;
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++width;
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if ((offset >= porta.size()) || (width >= op_outsigs[0].size()) || (width >= op_outsigs[1].size()))
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break;
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if ((porta[offset] != op_outsigs[0][width]) || (portb[offset] != op_outsigs[1][width]))
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break;
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}
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if (multi_user)
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return false;
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for (const auto &outsig : op_outsigs)
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for (int i = width; i < outsig.size(); i++)
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if (op_outbit_user_cnt.count(outsig[i]))
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return false;
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return true;
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}
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ExtSigSpec find_shared_operand(const std::vector<RTLIL::Cell *> &operators, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users)
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{
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std::set<RTLIL::Cell *> operators_set(operators.begin(), operators.end());
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ExtSigSpec oper;
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auto op_a = operators[0];
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for (auto &conn : op_a->connections()) {
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if (op_a->output(conn.first))
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if (offset >= ports[0]->sig.size()) {
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for (size_t i = 0; i < op_outsigs.size(); ++i) {
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if (finished[i])
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continue;
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oper = ExtSigSpec(op_a, conn.first, &assign_map);
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auto bundle = operand_to_users.at(oper);
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op_outsig_span[width].insert(ports[i]);
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finished[i] = true;
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}
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if (std::includes(bundle.begin(), bundle.end(), operators_set.begin(), operators_set.end()))
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break;
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}
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return oper;
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for (size_t i = 0; i < op_outsigs.size(); ++i) {
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if (finished[i])
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continue;
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if ((width >= op_outsigs[i].size()) || (ports[i]->sig[offset] != op_outsigs[i][width])) {
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op_outsig_span[width].insert(ports[i]);
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finished[i] = true;
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}
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}
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}
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for (auto w: op_outsig_span) {
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if (w.second.size() > 1) {
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width = w.first;
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ports.erase(std::remove_if(ports.begin(), ports.end(), [&](InPort *p) { return !w.second.count(p); }), ports.end());
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return true;
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}
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}
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return false;
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}
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dict<RTLIL::SigBit, int> find_op_outbit_user_cnt(RTLIL::Module *module, const dict<RTLIL::SigBit, RTLIL::SigSpec> &op_outbit_to_outsig)
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ExtSigSpec find_shared_operand(InPort* seed, std::vector<InPort *> &ports, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users)
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{
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std::set<RTLIL::Cell *> alus_using_operand;
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std::set<RTLIL::Cell *> alus_set;
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for(const auto& p: ports)
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alus_set.insert(p->alu);
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ExtSigSpec oper;
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auto op_a = seed->alu;
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for (RTLIL::IdString port_name : {"\\A", "\\B"}) {
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oper = ExtSigSpec(op_a, port_name, &assign_map);
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auto operand_users = operand_to_users.at(oper);
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if (operand_users.size() == 1)
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continue;
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alus_using_operand.clear();
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std::set_intersection(operand_users.begin(), operand_users.end(), alus_set.begin(), alus_set.end(),
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std::inserter(alus_using_operand, alus_using_operand.begin()));
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if (alus_using_operand.size() > 1) {
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ports.erase(std::remove_if(ports.begin(), ports.end(), [&](InPort *p) { return !alus_using_operand.count(p->alu); }),
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ports.end());
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return oper;
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}
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}
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return ExtSigSpec();
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}
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void remove_multi_user_outbits(RTLIL::Module *module, dict<RTLIL::SigBit, RTLIL::SigSpec> &op_outbit_to_outsig)
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{
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dict<RTLIL::SigBit, int> op_outbit_user_cnt;
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std::function<void(SigSpec)> update_op_outbit_user_cnt = [&](SigSpec sig) {
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auto outsig = assign_map(sig);
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for (auto outbit : outsig)
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if (op_outbit_to_outsig.count(outbit))
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op_outbit_user_cnt[outbit]++;
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for (auto outbit : outsig) {
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if (!op_outbit_to_outsig.count(outbit))
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continue;
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if (++op_outbit_user_cnt[outbit] > 1) {
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auto alu_outsig = op_outbit_to_outsig.at(outbit);
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for (auto outbit : alu_outsig)
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op_outbit_to_outsig.erase(outbit);
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}
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}
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};
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for (auto cell : module->cells())
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@ -216,8 +306,6 @@ dict<RTLIL::SigBit, int> find_op_outbit_user_cnt(RTLIL::Module *module, const di
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update_op_outbit_user_cnt(w);
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}
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return op_outbit_user_cnt;
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}
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struct OptRmdffPass : public Pass {
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@ -246,68 +334,110 @@ struct OptRmdffPass : public Pass {
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dict<RTLIL::SigSpec, RTLIL::Cell *> outsig_to_operator;
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dict<RTLIL::SigBit, RTLIL::SigSpec> op_outbit_to_outsig;
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bool any_shared_operands = false;
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std::vector<ExtSigSpec> op_insigs;
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for (auto cell : module->cells()) {
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if (!cell->type.in("$add", "$sub"))
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if (!cell->type.in("$alu"))
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continue;
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for (auto &conn : cell->connections()) {
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if (cell->output(conn.first)) {
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auto outsig = assign_map(conn.second);
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RTLIL::SigSpec sig_bi = cell->getPort("\\BI");
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RTLIL::SigSpec sig_ci = cell->getPort("\\CI");
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if ((!sig_bi.is_fully_const()) || (!sig_ci.is_fully_const()) || (sig_bi != sig_ci))
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continue;
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RTLIL::SigSpec sig_y = cell->getPort("\\A");
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auto outsig = assign_map(cell->getPort("\\Y"));
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outsig_to_operator[outsig] = cell;
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for (auto outbit : outsig)
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op_outbit_to_outsig[outbit] = outsig;
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outsig_to_operator[outsig] = cell;
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} else {
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auto op_insig = ExtSigSpec(cell, conn.first, &assign_map);
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for (RTLIL::IdString port_name : {"\\A", "\\B"}) {
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auto op_insig = ExtSigSpec(cell, port_name, &assign_map);
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op_insigs.push_back(op_insig);
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operand_to_users[op_insig].insert(cell);
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if (operand_to_users[op_insig].size() > 1)
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any_shared_operands = true;
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}
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}
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}
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if (!any_shared_operands)
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continue;
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// Operator outputs need to be exclusively connected to the $mux inputs in order to be mergeable. Hence we count to
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// how many points are operator output bits connected.
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dict<RTLIL::SigBit, int> op_outbit_user_cnt = find_op_outbit_user_cnt(module, op_outbit_to_outsig);
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remove_multi_user_outbits(module, op_outbit_to_outsig);
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std::vector<shared_op_t> shared_ops;
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for (auto cell : module->cells()) {
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if (!cell->type.in("$mux", "$_MUX_"))
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if (!cell->type.in("$mux", "$_MUX_", "$pmux"))
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continue;
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auto porta = assign_map(cell->getPort("\\A"));
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auto portb = assign_map(cell->getPort("\\B"));
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_s = cell->getPort("\\S");
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std::vector<InPort> ports;
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if (cell->type.in("$mux", "$_MUX_")) {
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ports.push_back(InPort(assign_map(sig_a), cell, 0));
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ports.push_back(InPort(assign_map(sig_b), cell, 1));
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} else {
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RTLIL::SigSpec sig_s = cell->getPort("\\S");
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for (int i = 0; i < sig_s.size(); i++) {
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auto inp = sig_b.extract(i * sig_a.size(), sig_a.size());
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ports.push_back(InPort(assign_map(inp), cell, i));
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}
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}
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// Look through the bits of the $mux inputs and see which of them are connected to the operator
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// results. Operator results can be concatenated with other signals before led to the $mux.
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for (int i = 0; i < porta.size(); ++i) {
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std::array<RTLIL::SigBit, 2> mux_inbits{porta[i], portb[i]};
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for (int i = 0; i < sig_a.size(); ++i) {
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std::vector<InPort*> alu_ports;
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for (auto& p: ports)
|
||||
if (op_outbit_to_outsig.count(p.sig[i])) {
|
||||
p.alu = outsig_to_operator.at(op_outbit_to_outsig.at(p.sig[i]));
|
||||
alu_ports.push_back(&p);
|
||||
}
|
||||
|
||||
// Are the results of an $add or $sub operators connected to both of this $mux inputs?
|
||||
if (!op_outbit_to_outsig.count(mux_inbits[0]) or !op_outbit_to_outsig.count(mux_inbits[1]))
|
||||
continue;
|
||||
int alu_port_width = 0;
|
||||
|
||||
std::vector<RTLIL::Cell *> operators;
|
||||
for (const auto &b : mux_inbits)
|
||||
operators.push_back(outsig_to_operator.at(op_outbit_to_outsig.at(b)));
|
||||
while (alu_ports.size() > 1) {
|
||||
std::vector<InPort*> shared_ports(alu_ports);
|
||||
|
||||
auto seed = alu_ports[0];
|
||||
alu_ports.erase(alu_ports.begin());
|
||||
|
||||
// Find ports whose $alu-s share an operand with $alu connected to the seed port
|
||||
auto shared_operand = find_shared_operand(seed, shared_ports, operand_to_users);
|
||||
|
||||
// Do these operators share an operand?
|
||||
auto shared_operand = find_shared_operand(operators, operand_to_users);
|
||||
if (shared_operand.empty())
|
||||
continue;
|
||||
|
||||
// Some bits of the operator results might be unconnected. Calculate the number of conneted
|
||||
// bits.
|
||||
int width;
|
||||
if (!find_op_res_width(i, alu_port_width, shared_ports, op_outbit_to_outsig))
|
||||
break;
|
||||
|
||||
if (find_op_res_width(i, width, porta, portb, op_outbit_to_outsig, op_outbit_user_cnt))
|
||||
shared_ops.push_back(shared_op_t{cell, operators, i, width, shared_operand});
|
||||
if (shared_ports.size() < 2)
|
||||
break;
|
||||
|
||||
i += width - 1;
|
||||
// Remember the combination for the merger
|
||||
std::vector<InPort> shared_p;
|
||||
for (auto p: shared_ports)
|
||||
shared_p.push_back(*p);
|
||||
|
||||
shared_ops.push_back(shared_op_t{cell, shared_p, i, alu_port_width, shared_operand});
|
||||
|
||||
// Remove merged ports from the list and try to find other mergers for the mux
|
||||
remove_val(alu_ports, shared_ports);
|
||||
}
|
||||
|
||||
if (alu_port_width)
|
||||
i += alu_port_width - 1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for (auto &shared : shared_ops) {
|
||||
|
|
@ -315,11 +445,11 @@ struct OptRmdffPass : public Pass {
|
|||
"of "
|
||||
"them:\n",
|
||||
log_id(shared.mux->type), log_id(shared.mux));
|
||||
for (auto op : shared.operators)
|
||||
log(" %s\n", log_id(op));
|
||||
for (const auto& op : shared.ports)
|
||||
log(" %s\n", log_id(op.alu));
|
||||
log("\n");
|
||||
|
||||
merge_operators(module, shared.mux, shared.operators, shared.offset, shared.width, shared.shared_operand);
|
||||
merge_operators(module, shared.mux, shared.ports, shared.offset, shared.width, shared.shared_operand);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,10 @@
|
|||
module opt_share_test(
|
||||
input [15:0] a,
|
||||
input [15:0] b,
|
||||
input sel,
|
||||
output [15:0] res,
|
||||
);
|
||||
|
||||
assign res = {sel ? a + b : a - b};
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog opt_share_add_sub.v
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
alumacc merged
|
||||
opt merged
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 1 -module merged t:$alu
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
module add_sub(
|
||||
module opt_share_test(
|
||||
input [15:0] a,
|
||||
input [15:0] b,
|
||||
input [15:0] c,
|
||||
|
|
|
|||
|
|
@ -1,9 +1,13 @@
|
|||
read_verilog opt_share_cat.v
|
||||
prep -flatten
|
||||
opt
|
||||
pmuxtree
|
||||
opt_share
|
||||
opt_clean
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
select -assert-count 2 t:$sub
|
||||
select -assert-count 0 t:$add
|
||||
alumacc merged
|
||||
opt merged
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 2 -module merged t:$alu
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
module opt_share_test(
|
||||
input [15:0] a,
|
||||
input [15:0] b,
|
||||
input [15:0] c,
|
||||
input [15:0] d,
|
||||
input sel,
|
||||
output reg [47:0] res,
|
||||
);
|
||||
|
||||
wire [15:0] add_res = a+b;
|
||||
wire [15:0] sub_res = a-b;
|
||||
wire [31: 0] cat1 = {add_res, c+d};
|
||||
wire [31: 0] cat2 = {sub_res, c-d};
|
||||
|
||||
always @* begin
|
||||
case(sel)
|
||||
0: res = {cat1, add_res};
|
||||
1: res = {cat2, add_res};
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog opt_share_cat_multiuser.v
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
alumacc merged
|
||||
opt merged
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 3 -module merged t:$alu
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
module opt_share_test(
|
||||
input [15:0] a,
|
||||
input [15:0] b,
|
||||
input [15:0] c,
|
||||
input [1:0] sel,
|
||||
output reg [15:0] res
|
||||
);
|
||||
|
||||
wire [15:0] add0_res = a+b;
|
||||
wire [15:0] add1_res = a+c;
|
||||
|
||||
always @* begin
|
||||
case(sel)
|
||||
0: res = add0_res[10:0];
|
||||
1: res = add1_res[10:0];
|
||||
2: res = a - b;
|
||||
default: res = 32'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog opt_share_diff_port_widths.v
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
alumacc merged
|
||||
opt merged
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 2 -module merged t:$alu
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
module opt_share_test(
|
||||
input signed [7:0] a,
|
||||
input signed [10:0] b,
|
||||
input signed [15:0] c,
|
||||
input [1:0] sel,
|
||||
output reg signed [15:0] res
|
||||
);
|
||||
|
||||
|
||||
always @* begin
|
||||
case(sel)
|
||||
0: res = a + b;
|
||||
1: res = a - b;
|
||||
2: res = a + c;
|
||||
default: res = 16'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog opt_share_extend.v
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
alumacc merged
|
||||
opt merged
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 1 -module merged t:$alu
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
module opt_share_test(
|
||||
input [15:0] a,
|
||||
input [15:0] b,
|
||||
input [15:0] c,
|
||||
input [2:0] sel,
|
||||
output reg [31:0] res
|
||||
);
|
||||
|
||||
|
||||
always @* begin
|
||||
case(sel)
|
||||
0: res = {a + b, a};
|
||||
1: res = {a - b, b};
|
||||
2: res = {a + c, c};
|
||||
3: res = {a - c, a};
|
||||
4: res = {b, b};
|
||||
5: res = {c, c};
|
||||
default: res = 32'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog opt_share_large_pmux_cat.v
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
alumacc merged
|
||||
opt merged
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 1 -module merged t:$alu
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
module opt_share_test(
|
||||
input [15:0] a,
|
||||
input [15:0] b,
|
||||
input [15:0] c,
|
||||
input [15:0] d,
|
||||
input [2:0] sel,
|
||||
output reg [31:0] res
|
||||
);
|
||||
|
||||
wire [15:0] add0_res = a+d;
|
||||
|
||||
always @* begin
|
||||
case(sel)
|
||||
0: res = {add0_res, a};
|
||||
1: res = {a - b, add0_res[7], 15'b0};
|
||||
2: res = {b-a, b};
|
||||
3: res = {d, b - c};
|
||||
4: res = {d, b - a};
|
||||
5: res = {c, d};
|
||||
6: res = {a - c, b-d};
|
||||
default: res = 32'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
read_verilog opt_share_large_pmux_cat_multipart.v
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
alumacc merged
|
||||
opt merged
|
||||
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 4 -module merged t:$alu
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
module opt_share_test(
|
||||
input [15:0] a,
|
||||
input [15:0] b,
|
||||
input [15:0] c,
|
||||
input [15:0] d,
|
||||
input [2:0] sel,
|
||||
output reg [15:0] res
|
||||
);
|
||||
|
||||
|
||||
always @* begin
|
||||
case(sel)
|
||||
0: res = a + d;
|
||||
1: res = a - b;
|
||||
2: res = b;
|
||||
3: res = b - c;
|
||||
4: res = b - a;
|
||||
5: res = c;
|
||||
6: res = a - c;
|
||||
default: res = 16'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog opt_share_large_pmux_multipart.v
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
alumacc merged
|
||||
opt merged
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 2 -module merged t:$alu
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
module opt_share_test(
|
||||
input [15:0] a,
|
||||
input [15:0] b,
|
||||
input [15:0] c,
|
||||
input [2:0] sel,
|
||||
output reg [15:0] res
|
||||
);
|
||||
|
||||
|
||||
always @* begin
|
||||
case(sel)
|
||||
0: res = a + b;
|
||||
1: res = a - b;
|
||||
2: res = a + c;
|
||||
3: res = a - c;
|
||||
4: res = b;
|
||||
5: res = c;
|
||||
default: res = 16'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
read_verilog opt_share_large_pmux_part.v
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
alumacc merged
|
||||
opt merged
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 1 -module merged t:$alu
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
module add_sub(
|
||||
module opt_share_test(
|
||||
input [15:0] a,
|
||||
input [15:0] b,
|
||||
input [15:0] c,
|
||||
|
|
|
|||
|
|
@ -1,10 +1,13 @@
|
|||
read_verilog opt_share_mux_tree.v
|
||||
prep -flatten
|
||||
opt
|
||||
pmuxtree
|
||||
opt_share;
|
||||
opt_share;
|
||||
opt_clean
|
||||
proc;;
|
||||
copy opt_share_test merged
|
||||
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 0 t:$sub
|
||||
alumacc merged
|
||||
opt merged
|
||||
opt_share merged
|
||||
opt_clean merged
|
||||
|
||||
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
||||
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
||||
|
||||
select -assert-count 1 -module merged t:$alu
|
||||
|
|
|
|||
Loading…
Reference in New Issue