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manual: fix typos.

This commit is contained in:
whitequark 2018-12-20 07:59:40 +00:00
parent a9ff81dd82
commit c04908c997
1 changed files with 2 additions and 2 deletions
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manual/CHAPTER_CellLib.tex
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@ -254,7 +254,7 @@ enable bit for each data bit), an address input \B{ADDR} and a data input
\begin{itemize} \begin{itemize}
\item \B{MEMID} \\ \item \B{MEMID} \\
The name of the RTLIL::Memory object that is associated with this read port. The name of the RTLIL::Memory object that is associated with this write port.
\item \B{ABITS} \\ \item \B{ABITS} \\
The number of address bits (width of the \B{ADDR} input port). The number of address bits (width of the \B{ADDR} input port).
@ -263,7 +263,7 @@ The number of address bits (width of the \B{ADDR} input port).
The number of data bits (width of the \B{DATA} output port). The number of data bits (width of the \B{DATA} output port).
\item \B{CLK\_ENABLE} \\ \item \B{CLK\_ENABLE} \\
When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and When this parameter is non-zero, the clock is used. Otherwise this write port is asynchronous and
the \B{CLK} input is not used. the \B{CLK} input is not used.
\item \B{CLK\_POLARITY} \\ \item \B{CLK\_POLARITY} \\