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Merge pull request #397 from azonenberg/gpak-libfixes 

Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're…
This commit is contained in:
Clifford Wolf 2017-08-30 11:53:44 +02:00 committed by GitHub
parent 8530333439 c3145863e7
commit c0034f51e6
1 changed files with 36 additions and 36 deletions
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72
techlibs/greenpak4/cells_sim_digital.v
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@ -147,7 +147,15 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
"RISING": begin "RISING": begin
always @(posedge CLK, posedge RST) begin always @(posedge CLK, posedge RST) begin
if(KEEP) begin //Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end end
else if(UP) begin else if(UP) begin
count <= count + 1'd1; count <= count + 1'd1;
@ -161,21 +169,21 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO; count <= COUNT_TO;
end end
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
end end
end end
"FALLING": begin "FALLING": begin
always @(posedge CLK, negedge RST) begin always @(posedge CLK, negedge RST) begin
if(KEEP) begin //Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end end
else if(UP) begin else if(UP) begin
count <= count + 1'd1; count <= count + 1'd1;
@ -189,14 +197,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO; count <= COUNT_TO;
end end
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
end end
end end
@ -286,8 +286,16 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
"RISING": begin "RISING": begin
always @(posedge CLK, posedge RST) begin always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter //Main counter
if(KEEP) begin else if(KEEP) begin
end end
else if(UP) begin else if(UP) begin
count <= count + 1'd1; count <= count + 1'd1;
@ -301,22 +309,22 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO; count <= COUNT_TO;
end end
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
end end
end end
"FALLING": begin "FALLING": begin
always @(posedge CLK, negedge RST) begin always @(posedge CLK, negedge RST) begin
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter //Main counter
if(KEEP) begin else if(KEEP) begin
end end
else if(UP) begin else if(UP) begin
count <= count + 1'd1; count <= count + 1'd1;
@ -330,14 +338,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO; count <= COUNT_TO;
end end
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
end end
end end