mirror of https://github.com/YosysHQ/yosys.git
proc_clean: only consider fully-defined case operands.
This commit is contained in:
parent
40978971f4
commit
bf84861fc2
|
@ -41,7 +41,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
|
||||||
break;
|
break;
|
||||||
for (int j = 0; j < int(cs->compare.size()); j++) {
|
for (int j = 0; j < int(cs->compare.size()); j++) {
|
||||||
RTLIL::SigSpec &val = cs->compare[j];
|
RTLIL::SigSpec &val = cs->compare[j];
|
||||||
if (!val.is_fully_const())
|
if (!val.is_fully_def())
|
||||||
continue;
|
continue;
|
||||||
if (val == sw->signal) {
|
if (val == sw->signal) {
|
||||||
cs->compare.clear();
|
cs->compare.clear();
|
||||||
|
|
|
@ -0,0 +1,22 @@
|
||||||
|
read_rtlil <<EOT
|
||||||
|
|
||||||
|
module \m
|
||||||
|
wire width 1 \w
|
||||||
|
process $p
|
||||||
|
switch 3'001
|
||||||
|
case 3'--1
|
||||||
|
assign \w 3'001
|
||||||
|
case 3'-1-
|
||||||
|
assign \w 3'010
|
||||||
|
case 3'1--
|
||||||
|
assign \w 3'100
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
EOT
|
||||||
|
|
||||||
|
proc_clean # Bug: removes the cases.
|
||||||
|
proc_clean # Removes the now-empty switch and its containing process.
|
||||||
|
|
||||||
|
select -assert-count 1 */p:*
|
Loading…
Reference in New Issue