mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
This commit is contained in:
commit
bf7d36627e
|
@ -58,7 +58,7 @@ struct ClkPartPass : public Pass {
|
||||||
}
|
}
|
||||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||||
{
|
{
|
||||||
log_header(design, "Executing CLKPART pass (TODO).\n");
|
log_header(design, "Executing CLKPART pass (partition design according to clock domain).\n");
|
||||||
log_push();
|
log_push();
|
||||||
|
|
||||||
clear_flags();
|
clear_flags();
|
||||||
|
@ -233,15 +233,16 @@ struct ClkPartPass : public Pass {
|
||||||
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
|
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
|
||||||
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
|
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
|
||||||
|
|
||||||
for (auto &it : assigned_cells) {
|
if (assigned_cells.size() > 1)
|
||||||
RTLIL::Selection sel(false);
|
for (auto &it : assigned_cells) {
|
||||||
sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
|
RTLIL::Selection sel(false);
|
||||||
|
sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
|
||||||
|
|
||||||
RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
|
RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
|
||||||
Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
|
Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
|
||||||
|
|
||||||
design->module(submod)->set_bool_attribute(ID(clkpart));
|
design->module(submod)->set_bool_attribute(ID(clkpart));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue