diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 1234ce1b2..554e2e13f 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -1,49 +1,3 @@
-module GP_DFF(input D, CLK, output reg Q);
-	parameter [0:0] INIT = 1'bx;
-	initial Q = INIT;
-	always @(posedge CLK) begin
-		Q <= D;
-	end
-endmodule
-
-module GP_DFFS(input D, CLK, nSET, output reg Q);
-	parameter [0:0] INIT = 1'bx;
-	initial Q = INIT;
-	always @(posedge CLK, negedge nSET) begin
-		if (!nSET)
-			Q <= 1'b1;
-		else
-			Q <= D;
-	end
-endmodule
-
-module GP_DFFR(input D, CLK, nRST, output reg Q);
-	parameter [0:0] INIT = 1'bx;
-	initial Q = INIT;
-	always @(posedge CLK, negedge nRST) begin
-		if (!nRST)
-			Q <= 1'b0;
-		else
-			Q <= D;
-	end
-endmodule
-
-module GP_DFFSR(input D, CLK, nSR, output reg Q);
-	parameter [0:0] INIT = 1'bx;
-	parameter [0:0] SRMODE = 1'bx;
-	initial Q = INIT;
-	always @(posedge CLK, negedge nSR) begin
-		if (!nSR)
-			Q <= SRMODE;
-		else
-			Q <= D;
-	end
-endmodule
-
-module GP_INV(input IN, output OUT);
-	assign OUT = ~IN;
-endmodule
-
 module GP_2LUT(input IN0, IN1, output OUT);
 	parameter [3:0] INIT = 0;
 	assign OUT = INIT[{IN1, IN0}];
@@ -59,62 +13,12 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
 	assign OUT = INIT[{IN3, IN2, IN1, IN0}];
 endmodule
 
-module GP_VDD(output OUT);
-       assign OUT = 1;
-endmodule
-
-module GP_VSS(output OUT);
-       assign OUT = 0;
-endmodule
-
-module GP_LFOSC(input PWRDN, output reg CLKOUT);
+module GP_BANDGAP(output reg OK, output reg VOUT);
+	parameter AUTO_PWRDN = 1;
+	parameter CHOPPER_EN = 1;
+	parameter OUT_DELAY = 100;
 	
-	parameter PWRDN_EN = 0;
-	parameter AUTO_PWRDN = 0;
-	parameter OUT_DIV = 1;
-	
-	initial CLKOUT = 0;
-	
-	//auto powerdown not implemented for simulation
-	//output dividers not implemented for simulation
-	
-	always begin
-		if(PWRDN)
-			CLKOUT = 0;
-		else begin
-			//half period of 1730 Hz
-			#289017;
-			CLKOUT = ~CLKOUT;
-		end
-	end
-	
-endmodule
-
-module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
-	
-	parameter PWRDN_EN = 0;
-	parameter AUTO_PWRDN = 0;
-	parameter PRE_DIV = 1;
-	parameter FABRIC_DIV = 1;
-	
-	initial CLKOUT_PREDIV = 0;
-	initial CLKOUT_FABRIC = 0;
-	
-	//output dividers not implemented for simulation
-	//auto powerdown not implemented for simulation
-	
-	always begin
-		if(PWRDN) begin
-			CLKOUT_PREDIV = 0;
-			CLKOUT_FABRIC = 0;
-		end
-		else begin
-			//half period of 27 MHz
-			#18.518;
-			CLKOUT_PREDIV = ~CLKOUT_PREDIV;
-			CLKOUT_FABRIC = ~CLKOUT_FABRIC;
-		end
-	end
+	//cannot simulate mixed signal IP
 	
 endmodule
 
@@ -167,24 +71,74 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
 endmodule
 
-//keep constraint needed to prevent optimization since we have no outputs
-(* keep *)
-module GP_SYSRESET(input RST);
-	parameter RESET_MODE = "RISING";
-	
-	//cannot simulate whole system reset
-	
+module GP_DFF(input D, CLK, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(posedge CLK) begin
+		Q <= D;
+	end
 endmodule
 
-module GP_BANDGAP(output reg OK, output reg VOUT);
-	parameter AUTO_PWRDN = 1;
-	parameter CHOPPER_EN = 1;
-	parameter OUT_DELAY = 100;
-	
-	//cannot simulate mixed signal IP
-	
+module GP_DFFR(input D, CLK, nRST, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(posedge CLK, negedge nRST) begin
+		if (!nRST)
+			Q <= 1'b0;
+		else
+			Q <= D;
+	end
 endmodule
 
+module GP_DFFS(input D, CLK, nSET, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(posedge CLK, negedge nSET) begin
+		if (!nSET)
+			Q <= 1'b1;
+		else
+			Q <= D;
+	end
+endmodule
+
+module GP_DFFSR(input D, CLK, nSR, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	parameter [0:0] SRMODE = 1'bx;
+	initial Q = INIT;
+	always @(posedge CLK, negedge nSR) begin
+		if (!nSR)
+			Q <= SRMODE;
+		else
+			Q <= D;
+	end
+endmodule
+
+module GP_INV(input IN, output OUT);
+	assign OUT = ~IN;
+endmodule
+
+module GP_LFOSC(input PWRDN, output reg CLKOUT);
+	
+	parameter PWRDN_EN = 0;
+	parameter AUTO_PWRDN = 0;
+	parameter OUT_DIV = 1;
+	
+	initial CLKOUT = 0;
+	
+	//auto powerdown not implemented for simulation
+	//output dividers not implemented for simulation
+	
+	always begin
+		if(PWRDN)
+			CLKOUT = 0;
+		else begin
+			//half period of 1730 Hz
+			#289017;
+			CLKOUT = ~CLKOUT;
+		end
+	end
+	
+endmodule
 
 module GP_POR(output reg RST_DONE);
 	parameter POR_TIME = 500;
@@ -206,3 +160,109 @@ module GP_POR(output reg RST_DONE);
 	end
 	
 endmodule
+
+module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
+	
+	parameter PWRDN_EN = 0;
+	parameter AUTO_PWRDN = 0;
+	parameter PRE_DIV = 1;
+	parameter FABRIC_DIV = 1;
+	parameter OSC_FREQ = "25k";
+	
+	initial CLKOUT_PREDIV = 0;
+	initial CLKOUT_FABRIC = 0;
+	
+	//output dividers not implemented for simulation
+	//auto powerdown not implemented for simulation
+	
+	always begin
+		if(PWRDN) begin
+			CLKOUT_PREDIV = 0;
+			CLKOUT_FABRIC = 0;
+		end
+		else begin
+		
+			if(OSC_FREQ == "25k") begin
+				//half period of 25 kHz
+				#20000;
+			end
+			
+			else begin
+				//half period of 2 MHz
+				#250;
+			end
+			
+			CLKOUT_PREDIV = ~CLKOUT_PREDIV;
+			CLKOUT_FABRIC = ~CLKOUT_FABRIC;
+		end
+	end
+	
+endmodule
+
+module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
+	
+	parameter PWRDN_EN = 0;
+	parameter AUTO_PWRDN = 0;
+	parameter PRE_DIV = 1;
+	parameter FABRIC_DIV = 1;
+	
+	initial CLKOUT_PREDIV = 0;
+	initial CLKOUT_FABRIC = 0;
+	
+	//output dividers not implemented for simulation
+	//auto powerdown not implemented for simulation
+	
+	always begin
+		if(PWRDN) begin
+			CLKOUT_PREDIV = 0;
+			CLKOUT_FABRIC = 0;
+		end
+		else begin
+			//half period of 27 MHz
+			#18.518;
+			CLKOUT_PREDIV = ~CLKOUT_PREDIV;
+			CLKOUT_FABRIC = ~CLKOUT_FABRIC;
+		end
+	end
+	
+endmodule
+
+module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
+
+	parameter OUTA_DELAY = 1;
+	parameter OUTA_INVERT = 0;
+	parameter OUTB_DELAY = 1;
+	
+	reg[15:0] shreg = 0;
+	
+	always @(posedge clk, negedge RSTN) begin
+		
+		if(!nRST)
+			shreg = 0;
+		
+		else
+			shreg <= {shreg[14:0], IN};
+		
+	end
+	
+	assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
+	assign OUTB = shreg[OUTB_DELAY - 1];
+
+endmodule
+
+//keep constraint needed to prevent optimization since we have no outputs
+(* keep *)
+module GP_SYSRESET(input RST);
+	parameter RESET_MODE = "RISING";
+	
+	//cannot simulate whole system reset
+	
+endmodule
+
+module GP_VDD(output OUT);
+       assign OUT = 1;
+endmodule
+
+module GP_VSS(output OUT);
+       assign OUT = 0;
+endmodule