mirror of https://github.com/YosysHQ/yosys.git
Remove mapped_mod when done
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@ -937,6 +937,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
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//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
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log("ABC RESULTS: input signals: %8d\n", in_wires);
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log("ABC RESULTS: input signals: %8d\n", in_wires);
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log("ABC RESULTS: output signals: %8d\n", out_wires);
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log("ABC RESULTS: output signals: %8d\n", out_wires);
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design->remove(mapped_mod);
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}
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}
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//else
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//else
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//{
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//{
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