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Conditioning abc9 on POs not accurate due to cells

This commit is contained in:
Eddie Hung 2019-11-23 10:26:55 -08:00
parent eb11c06a69
commit bf1167bc64
1 changed files with 6 additions and 15 deletions
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21
passes/techmap/abc9.cc
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@ -322,19 +322,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
fprintf(f, "%s\n", abc9_script.c_str()); fprintf(f, "%s\n", abc9_script.c_str());
fclose(f); fclose(f);
bool count_output = false; //bool count_output = false;
for (auto port_name : module->ports) {
RTLIL::Wire *port_wire = module->wire(port_name);
log_assert(port_wire);
if (port_wire->port_output) {
count_output = true;
break;
}
}
log_push(); log_push();
if (count_output) //if (count_output)
{ {
handle_loops(design, module); handle_loops(design, module);
@ -736,10 +727,10 @@ clone_lut:
design->remove(mapped_mod); design->remove(mapped_mod);
} }
else //else
{ //{
log("Don't call ABC as there is nothing to map.\n"); // log("Don't call ABC as there is nothing to map.\n");
} //}
if (cleanup) if (cleanup)
{ {