mirror of https://github.com/YosysHQ/yosys.git
no support for 6-series xilinx devices
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@ -44,7 +44,7 @@ struct SynthXilinxPass : public Pass {
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log("\n");
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log("\n");
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log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
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log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
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log("partly selected designs. At the moment this command creates netlists that are\n");
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log("partly selected designs. At the moment this command creates netlists that are\n");
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log("compatible with 7-series and 6-series Xilinx devices.\n");
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log("compatible with 7-Series Xilinx devices.\n");
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log("\n");
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log("\n");
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log(" -top <module>\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log(" use the specified module as top module (default='top')\n");
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