Merge pull request #1687 from YosysHQ/eddie/fix_ystests

Fix shiftx2mux, fix yosys-tests
This commit is contained in:
Eddie Hung 2020-02-07 12:32:08 -08:00 committed by GitHub
commit be8bc63f84
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 7 additions and 9 deletions

View File

@ -471,7 +471,7 @@ struct Abc9ExePass : public Pass {
// handle -lut / -luts args
if (!lut_arg.empty()) {
string arg = lut_arg;
if (arg.find_first_not_of("0123456789:") == std::string::npos) {
if (arg.find_first_not_of("0123456789:,") == std::string::npos) {
size_t pos = arg.find_first_of(':');
int lut_mode = 0, lut_mode2 = 0;
if (pos != string::npos) {

View File

@ -149,16 +149,14 @@ module _90_shift_shiftx (A, B, Y);
_TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin
// Halve the size of $shift/$shiftx by $mux-ing A according to
// the LSB of B, after discarding the zeroed bits
localparam len = 2**(B_WIDTH-1);
localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
wire [len-1:0] T, F, AA;
wire [(A_WIDTH+Y_WIDTH2*2):0] Apad = {{Y_WIDTH2*2{extbit}}, A};
localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2;
localparam len = Y_WIDTH2 * ((entries+1)/2);
wire [len-1:0] AA;
wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A};
genvar i;
for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin
assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2];
assign T[i/2 +: Y_WIDTH2] = Apad[i+Y_WIDTH2 +: Y_WIDTH2];
assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2];
end
for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2)
assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2];
wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
if (_TECHMAP_CELLTYPE_ == "$shift")
$shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));