From be752a20dce72a409a05072e9d6055361b52335a Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 30 Nov 2022 18:49:16 +0100 Subject: [PATCH] Add bwmuxmap pass --- backends/btor/btor.cc | 1 + backends/firrtl/firrtl.cc | 1 + backends/smt2/smt2.cc | 1 + backends/smv/smv.cc | 1 + backends/verilog/verilog_backend.cc | 1 + passes/techmap/Makefile.inc | 1 + passes/techmap/bwmuxmap.cc | 70 +++++++++++++++++++++++++++++ 7 files changed, 76 insertions(+) create mode 100644 passes/techmap/bwmuxmap.cc diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 06de71018..8368ab82d 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1417,6 +1417,7 @@ struct BtorBackend : public Backend { log_push(); Pass::call(design, "bmuxmap"); Pass::call(design, "demuxmap"); + Pass::call(design, "bwmuxmap"); log_pop(); size_t argidx; diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 76ba77abb..e483117d1 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -1215,6 +1215,7 @@ struct FirrtlBackend : public Backend { Pass::call(design, "pmuxtree"); Pass::call(design, "bmuxmap"); Pass::call(design, "demuxmap"); + Pass::call(design, "bwmuxmap"); namecache.clear(); autoid_counter = 0; diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 7434b13da..fe50ca7f6 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -1744,6 +1744,7 @@ struct Smt2Backend : public Backend { log_push(); Pass::call(design, "bmuxmap"); Pass::call(design, "demuxmap"); + Pass::call(design, "bwmuxmap"); log_pop(); size_t argidx; diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index 7d4f94adc..49c2cc7a6 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -744,6 +744,7 @@ struct SmvBackend : public Backend { log_push(); Pass::call(design, "bmuxmap"); Pass::call(design, "demuxmap"); + Pass::call(design, "bwmuxmap"); log_pop(); size_t argidx; diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 3da168960..0a9c0590e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2329,6 +2329,7 @@ struct VerilogBackend : public Backend { if (!noexpr) { Pass::call(design, "bmuxmap"); Pass::call(design, "demuxmap"); + Pass::call(design, "bwmuxmap"); } Pass::call(design, "clean_zerowidth"); log_pop(); diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 98ccfc303..1b834fabc 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -31,6 +31,7 @@ OBJS += passes/techmap/dffinit.o OBJS += passes/techmap/pmuxtree.o OBJS += passes/techmap/bmuxmap.o OBJS += passes/techmap/demuxmap.o +OBJS += passes/techmap/bwmuxmap.o OBJS += passes/techmap/muxcover.o OBJS += passes/techmap/aigmap.o OBJS += passes/techmap/tribuf.o diff --git a/passes/techmap/bwmuxmap.cc b/passes/techmap/bwmuxmap.cc new file mode 100644 index 000000000..7fe1cded7 --- /dev/null +++ b/passes/techmap/bwmuxmap.cc @@ -0,0 +1,70 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2022 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct BwmuxmapPass : public Pass { + BwmuxmapPass() : Pass("bwmuxmap", "replace $bwmux cells with equivalent logic") {} + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" bwmxumap [options] [selection]\n"); + log("\n"); + log("This pass replaces $bwmux cells with equivalent logic\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing BWMUXMAP pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + // if (args[argidx] == "-arg") { + // continue; + // } + break; + } + + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + for (auto cell : module->selected_cells()) + { + if (cell->type != ID($bwmux)) + continue; + auto &sig_y = cell->getPort(ID::Y); + auto &sig_a = cell->getPort(ID::A); + auto &sig_b = cell->getPort(ID::B); + auto &sig_s = cell->getPort(ID::S); + + auto not_s = module->Not(NEW_ID, sig_s); + auto masked_b = module->And(NEW_ID, sig_s, sig_b); + auto masked_a = module->And(NEW_ID, not_s, sig_a); + module->addOr(NEW_ID, masked_a, masked_b, sig_y); + + module->remove(cell); + } + } +} BwmuxmapPass; + +PRIVATE_NAMESPACE_END