riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig

This commit is contained in:
Eddie Hung 2019-02-21 09:31:17 -08:00
parent 7f26043caf 2da4c9c8f0
commit be061810d7
2 changed files with 7 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
passes/opt/opt_rmdff.cc
View File

@ -174,8 +174,6 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
cell->unsetParam("\\CLR_POLARITY"); cell->unsetParam("\\CLR_POLARITY");
cell->unsetPort("\\SET"); cell->unsetPort("\\SET");
cell->unsetPort("\\CLR"); cell->unsetPort("\\CLR");
return true;
} }
else else
{ {
@ -186,11 +184,12 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
cell->unsetParam("\\CLR_POLARITY"); cell->unsetParam("\\CLR_POLARITY");
cell->unsetPort("\\SET"); cell->unsetPort("\\SET");
cell->unsetPort("\\CLR"); cell->unsetPort("\\CLR");
}
return true; return true;
} }
}
else if (!hasreset)
{ {
IdString new_type; IdString new_type;
@ -207,8 +206,10 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
cell->unsetPort("\\S"); cell->unsetPort("\\S");
cell->unsetPort("\\R"); cell->unsetPort("\\R");
return did_something; return true;
} }
return did_something;
} }
bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)

21
tests/simple_defparam/run-test.sh
View File

@ -1,21 +0,0 @@
#!/bin/bash
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
cp ../simple/*.v .
exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-B \"-defparam\""