riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

peepopt: Clean up 'shiftmul' a bit 

No functional change intended.
This commit is contained in:
Martin Povišer 2023-08-02 15:44:41 +02:00
parent a0c3be3aae
commit bd8a81a907
1 changed files with 36 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
passes/pmgen/peepopt_shiftmul.pmg
View File

@ -3,61 +3,67 @@ pattern shiftmul
// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] // Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
// //
state <SigSpec> shamt
match shift match shift
select shift->type.in($shift, $shiftx, $shr) select shift->type.in($shift, $shiftx, $shr)
filter !port(shift, \B).empty()
endmatch endmatch
code shamt state <SigSpec> shift_amount
shamt = port(shift, \B);
if (shamt.empty()) code shift_amount
reject; shift_amount = port(shift, \B);
if (shamt[GetSize(shamt)-1] == State::S0) { if (shift->type.in($shr) || !param(shift, \B_SIGNED).as_bool())
do { shift_amount.append(State::S0);
shamt.remove(GetSize(shamt)-1);
if (shamt.empty()) // at this point shift_amount is signed, make
reject; // sure we can never go negative
} while (shamt[GetSize(shamt)-1] == State::S0); if (shift_amount.bits().back() != State::S0)
} else
if (shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool()) {
reject; reject;
while (shift_amount.bits().back() == State::S0) {
shift_amount.remove(GetSize(shift_amount) - 1);
if (shift_amount.empty()) reject;
} }
if (GetSize(shamt) > 20)
if (GetSize(shift_amount) > 20)
reject; reject;
endcode endcode
state <SigSpec> mul_din
state <Const> mul_const
match mul match mul
select mul->type.in($mul) select mul->type.in($mul)
select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const() index <SigSpec> port(mul, \Y) === shift_amount
index <SigSpec> port(mul, \Y) === shamt
filter !param(mul, \A_SIGNED).as_bool() filter !param(mul, \A_SIGNED).as_bool()
choice <IdString> constport {\A, \B}
filter port(mul, constport).is_fully_const()
define <IdString> varport (constport == \A ? \B : \A)
set mul_const port(mul, constport).as_const()
set mul_din port(mul, varport)
endmatch endmatch
code code
{ {
IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B; if (mul_const.empty() || GetSize(mul_const) > 20)
Const const_factor_cnst = port(mul, const_factor_port).as_const();
int const_factor = const_factor_cnst.as_int();
if (GetSize(const_factor_cnst) == 0)
reject; reject;
if (GetSize(const_factor_cnst) > 20) // make sure there's no overlap in the signal
// selections by the shiftmul pattern
if (GetSize(port(shift, \Y)) > mul_const.as_int())
reject; reject;
if (GetSize(port(shift, \Y)) > const_factor) int factor_bits = ceil_log2(mul_const.as_int());
reject; // make sure the multiplication never wraps around
if (GetSize(shift_amount) < factor_bits + GetSize(mul_din))
int factor_bits = ceil_log2(const_factor);
SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
if (GetSize(shamt) < factor_bits+GetSize(mul_din))
reject; reject;
did_something = true; did_something = true;
log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
int const_factor = mul_const.as_int();
int new_const_factor = 1 << factor_bits; int new_const_factor = 1 << factor_bits;
SigSpec padding(State::Sx, new_const_factor-const_factor); SigSpec padding(State::Sx, new_const_factor-const_factor);
SigSpec old_a = port(shift, \A), new_a; SigSpec old_a = port(shift, \A), new_a;