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rmports now works on all modules in the design, not just the top.

This commit is contained in:
Andrew Zonenberg 2017-08-14 11:16:44 -07:00
parent d5e5bbad86
commit bd2ac68769
1 changed files with 7 additions and 4 deletions
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11
passes/opt/rmports.cc
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@ -27,7 +27,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct RmportsPassPass : public Pass {
RmportsPassPass() : Pass("rmports", "remove top-level ports with no connections") { }
RmportsPassPass() : Pass("rmports", "remove module ports with no connections") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@ -42,7 +42,10 @@ struct RmportsPassPass : public Pass {
virtual void execute(std::vector<std::string> /*args*/, RTLIL::Design *design)
{
log_header(design, "Executing RMPORTS pass (remove top level ports with no connections).\n");
ProcessModule(design->top_module());
auto modules = design->selected_modules();
for(auto mod : modules)
ProcessModule(mod);
}
virtual void ProcessModule(RTLIL::Module* module)
@ -114,7 +117,7 @@ struct RmportsPassPass : public Pass {
//Print the ports out as we go through them
for(auto port : unused_ports)
{
log(" removing unused top-level port %s\n", port.c_str());
log(" removing unused port %s\n", port.c_str());
//Remove from ports list
for(size_t i=0; i<module->ports.size(); i++)
@ -132,7 +135,7 @@ struct RmportsPassPass : public Pass {
wire->port_output = false;
wire->port_id = 0;
}
log("Removed %zu unused top-level ports.\n", unused_ports.size());
log("Removed %zu unused ports.\n", unused_ports.size());
//Re-number all of the wires that DO have ports still on them
for(size_t i=0; i<module->ports.size(); i++)