From 567e5f0aa7816bf92e0f1cb885af6fa333863163 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 17:42:36 -0700
Subject: [PATCH 1/5] Fix first testcase in #1391

---
 passes/techmap/abc9.cc    | 2 +-
 passes/techmap/techmap.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 7eac08d17..7715fb291 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -30,7 +30,7 @@
 						"&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
 						"&mfs; &ps -l"
 #else
-#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
+#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v -w; &mfs; &ps -l"
 #endif
 
 
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index cf40b2f17..3cc3edbcb 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -224,7 +224,7 @@ struct TechmapWorker
 
 					for (auto bit : sigmaps.at(tpl)(it.second))
 						if (bit.wire != nullptr)
-							autopurge_tpl_bits.insert(it.second);
+							autopurge_tpl_bits.insert(bit);
 				}
 			}
 			IdString w_name = it.second->name;

From 72ce06909e87d1697ed5eac62d91db00a751a34b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 17:48:37 -0700
Subject: [PATCH 2/5] Trim mismatched connection to be same (smallest) size

---
 passes/techmap/techmap.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 3cc3edbcb..1d0362ad6 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -359,6 +359,12 @@ struct TechmapWorker
 				for (auto &attr : w->attributes) {
 					if (attr.first == ID(src))
 						continue;
+					auto lhs = GetSize(extra_connect.first);
+					auto rhs = GetSize(extra_connect.second);
+					if (lhs > rhs)
+						extra_connect.first.remove(rhs, lhs-rhs);
+					else if (rhs > lhs)
+						extra_connect.second.remove(lhs, rhs-lhs);
 					module->connect(extra_connect);
 					break;
 				}

From 6258e6a7e28ade2bdc7b6809675461326c873a45 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 17:49:26 -0700
Subject: [PATCH 3/5] Add testcase

---
 tests/techmap/autopurge.ys | 43 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 tests/techmap/autopurge.ys

diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys
new file mode 100644
index 000000000..4773d5ce3
--- /dev/null
+++ b/tests/techmap/autopurge.ys
@@ -0,0 +1,43 @@
+# https://github.com/YosysHQ/yosys/issues/1391
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+read_verilog -overwrite <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+wire j;
+sub s0(i, o, j);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy

From ec08a031b548749bc3177ed3fdddcaf463043d26 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 17:52:23 -0700
Subject: [PATCH 4/5] Revert abc9.cc

---
 passes/techmap/abc9.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 7715fb291..7eac08d17 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -30,7 +30,7 @@
 						"&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
 						"&mfs; &ps -l"
 #else
-#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v -w; &mfs; &ps -l"
+#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
 #endif
 
 

From 7c8de1dd180e4d6cf708700d73f29f3b581722ce Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 17:58:51 -0700
Subject: [PATCH 5/5] Hell let's add the original #1381 testcase too

---
 tests/techmap/autopurge.ys | 35 +++++++++++++++++++++++++++--------
 1 file changed, 27 insertions(+), 8 deletions(-)

diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys
index 4773d5ce3..1eb99ec37 100644
--- a/tests/techmap/autopurge.ys
+++ b/tests/techmap/autopurge.ys
@@ -1,4 +1,31 @@
+# https://github.com/YosysHQ/yosys/issues/1381
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
 # https://github.com/YosysHQ/yosys/issues/1391
+design -reset
 read_verilog <<EOT
 module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
 foobar f(i, o, j);
@@ -25,14 +52,6 @@ hierarchy
 check -assert
 
 read_verilog -overwrite <<EOT
-(* blackbox *)
-module sub(input i, output o, input j);
-endmodule
-
-(* blackbox *)
-module foobar(input i, output o, input j);
-endmodule
-
 module top(input i, output o);
 wire j;
 sub s0(i, o, j);