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Fixed some visual studio warnings

This commit is contained in:
Clifford Wolf 2016-02-13 17:31:24 +01:00
parent 6f1d694171
commit bcc873b805
8 changed files with 10 additions and 10 deletions
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2
frontends/ast/ast.cc
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@ -820,7 +820,7 @@ uint64_t AstNode::asInt(bool is_signed)
} }
if (type == AST_REALVALUE) if (type == AST_REALVALUE)
return realvalue; return uint64_t(realvalue);
log_abort(); log_abort();
} }

2
frontends/ast/genrtlil.cc
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@ -1257,7 +1257,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (type == AST_MEMINIT) { if (type == AST_MEMINIT) {
if (children[2]->type != AST_CONSTANT) if (children[2]->type != AST_CONSTANT)
log_error("Memory init with non-constant word count at %s:%d!\n", filename.c_str(), linenum); log_error("Memory init with non-constant word count at %s:%d!\n", filename.c_str(), linenum);
num_words = children[2]->asInt(false); num_words = int(children[2]->asInt(false));
cell->parameters["\\WORDS"] = RTLIL::Const(num_words); cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
} }

4
frontends/ast/simplify.cc
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@ -1705,7 +1705,7 @@ skip_dynamic_range_lvalue_expansion:;
while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (node_addr->type != AST_CONSTANT) if (node_addr->type != AST_CONSTANT)
log_error("Failed to evaluate system function `%s' with non-constant 3rd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_error("Failed to evaluate system function `%s' with non-constant 3rd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
start_addr = node_addr->asInt(false); start_addr = int(node_addr->asInt(false));
} }
if (GetSize(children) > 3) { if (GetSize(children) > 3) {
@ -1713,7 +1713,7 @@ skip_dynamic_range_lvalue_expansion:;
while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (node_addr->type != AST_CONSTANT) if (node_addr->type != AST_CONSTANT)
log_error("Failed to evaluate system function `%s' with non-constant 4th argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_error("Failed to evaluate system function `%s' with non-constant 4th argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
finish_addr = node_addr->asInt(false); finish_addr = int(node_addr->asInt(false));
} }
bool unconditional_init = false; bool unconditional_init = false;

2
kernel/hashlib.h
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@ -74,7 +74,7 @@ template<> struct hash_ops<int32_t> : hash_int_ops
template<> struct hash_ops<int64_t> : hash_int_ops template<> struct hash_ops<int64_t> : hash_int_ops
{ {
static inline unsigned int hash(int64_t a) { static inline unsigned int hash(int64_t a) {
return mkhash(a, a >> 32); return mkhash((unsigned int)(a), (unsigned int)(a >> 32));
} }
}; };

4
kernel/modtools.h
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@ -180,8 +180,8 @@ struct ModIndex : public RTLIL::Monitor
{ {
RTLIL::SigBit lhs = sigmap(sigsig.first[i]); RTLIL::SigBit lhs = sigmap(sigsig.first[i]);
RTLIL::SigBit rhs = sigmap(sigsig.second[i]); RTLIL::SigBit rhs = sigmap(sigsig.second[i]);
bool has_lhs = database.count(lhs); bool has_lhs = database.count(lhs) != 0;
bool has_rhs = database.count(rhs); bool has_rhs = database.count(rhs) != 0;
if (!has_lhs && !has_rhs) { if (!has_lhs && !has_rhs) {
sigmap.add(lhs, rhs); sigmap.add(lhs, rhs);

2
kernel/yosys.cc
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@ -193,7 +193,7 @@ std::string vstringf(const char *fmt, va_list ap)
int readsome(std::istream &f, char *s, int n) int readsome(std::istream &f, char *s, int n)
{ {
int rc = f.readsome(s, n); int rc = int(f.readsome(s, n));
// f.readsome() sometimes returns 0 on a non-empty stream.. // f.readsome() sometimes returns 0 on a non-empty stream..
if (rc == 0) { if (rc == 0) {

2
passes/memory/memory_dff.cc
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@ -164,7 +164,7 @@ struct MemoryDffWorker
if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)) if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
{ {
bool enable_invert = mux_cells_a.count(sig_data); bool enable_invert = mux_cells_a.count(sig_data) != 0;
Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
SigSpec check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")); SigSpec check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));

2
passes/techmap/techmap.cc
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@ -313,7 +313,7 @@ struct TechmapWorker
if (c->type == "$memrd" || c->type == "$memwr" || c->type == "$meminit") { if (c->type == "$memrd" || c->type == "$memwr" || c->type == "$meminit") {
IdString memid = c->getParam("\\MEMID").decode_string(); IdString memid = c->getParam("\\MEMID").decode_string();
log_assert(memory_renames.count(memid)); log_assert(memory_renames.count(memid) != 0);
c->setParam("\\MEMID", Const(memory_renames[memid].str())); c->setParam("\\MEMID", Const(memory_renames[memid].str()));
} }