From f06cb75b930d6ef5d8f4f12825ce0ef8f296ce17 Mon Sep 17 00:00:00 2001 From: Jakob Wenzel Date: Thu, 9 May 2019 12:37:31 +0200 Subject: [PATCH 1/5] initialize more registers in setundef -init --- passes/cmds/setundef.cc | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index f6949c820..5b43d528c 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -404,22 +404,29 @@ struct SetundefPass : public Pass { initwires.insert(wire); } - for (int wire_types = 0; wire_types < 2; wire_types++) - for (auto wire : module->wires()) - { - if (wire->name[0] == (wire_types ? '\\' : '$')) - next_wire: - continue; + for (int wire_types = 0; wire_types < 2; wire_types++) { + pool ffbitsToErase; + for (auto wire : module->wires()) { + if (wire->name[0] == (wire_types ? '\\' : '$')) { + next_wire: + continue; + } - for (auto bit : sigmap(wire)) - if (!ffbits.count(bit)) - goto next_wire; + for (auto bit : sigmap(wire)) + if (!ffbits.count(bit)) { + goto next_wire; + } - for (auto bit : sigmap(wire)) - ffbits.erase(bit); + for (auto bit : sigmap(wire)) { + ffbitsToErase.insert(bit); + } - initwires.insert(wire); - } + initwires.insert(wire); + } + for (const auto &bit : ffbitsToErase) { + ffbits.erase(bit); + } + } for (auto wire : initwires) { From dd3c333c0a206708ba2d821395fbf58a0e541f7b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 5 Jun 2019 08:57:33 +0200 Subject: [PATCH 2/5] Remove yosys_banner() from python wrapper init, fixes #1056 Signed-off-by: Clifford Wolf --- misc/py_wrap_generator.py | 1 - 1 file changed, 1 deletion(-) diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py index 09f934040..9f2c72915 100644 --- a/misc/py_wrap_generator.py +++ b/misc/py_wrap_generator.py @@ -2060,7 +2060,6 @@ namespace YOSYS_PYTHON { Yosys::log_streams.push_back(&std::cout); Yosys::log_error_stderr = true; Yosys::yosys_setup(); - Yosys::yosys_banner(); } } From 4190d7c09477f4bdd35cbd7bf5388254764b2321 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 5 Jun 2019 09:26:44 +0200 Subject: [PATCH 3/5] Fix typo in fmcombine log message, fixes #1063 Signed-off-by: Clifford Wolf --- passes/sat/fmcombine.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index f64d99dc2..00c098542 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -332,7 +332,7 @@ struct FmcombinePass : public Pass { gate_cell = module->cell(gate_name); if (gate_cell == nullptr) - log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gate_name), log_id(module)); + log_cmd_error("Gate cell %s not found in module %s.\n", log_id(gate_name), log_id(module)); } else { @@ -351,7 +351,7 @@ struct FmcombinePass : public Pass { if (!gold_cell->parameters.empty()) log_cmd_error("Gold cell has unresolved instance parameters.\n"); if (!gate_cell->parameters.empty()) - log_cmd_error("Gold cell has unresolved instance parameters.\n"); + log_cmd_error("Gate cell has unresolved instance parameters.\n"); FmcombineWorker worker(design, gold_cell->type, opts); worker.generate(); From 6cc60ffd67784fa74e3ccbf9c2c273ad610e14b2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 5 Jun 2019 09:53:06 +0200 Subject: [PATCH 4/5] Indent fix Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 42 +++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 5b43d528c..e46d0a1dc 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -404,29 +404,31 @@ struct SetundefPass : public Pass { initwires.insert(wire); } - for (int wire_types = 0; wire_types < 2; wire_types++) { - pool ffbitsToErase; - for (auto wire : module->wires()) { - if (wire->name[0] == (wire_types ? '\\' : '$')) { - next_wire: - continue; - } + for (int wire_types = 0; wire_types < 2; wire_types++) + { + pool ffbitsToErase; + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) { + next_wire: + continue; + } - for (auto bit : sigmap(wire)) - if (!ffbits.count(bit)) { - goto next_wire; - } + for (auto bit : sigmap(wire)) + if (!ffbits.count(bit)) { + goto next_wire; + } - for (auto bit : sigmap(wire)) { - ffbitsToErase.insert(bit); - } + for (auto bit : sigmap(wire)) { + ffbitsToErase.insert(bit); + } - initwires.insert(wire); - } - for (const auto &bit : ffbitsToErase) { - ffbits.erase(bit); - } - } + initwires.insert(wire); + } + for (const auto & bit : ffbitsToErase) { + ffbits.erase(bit); + } + } for (auto wire : initwires) { From b33176dafb03589952d3ac425e7cd8eeec61ea6a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 5 Jun 2019 10:26:48 +0200 Subject: [PATCH 5/5] Major rewrite of wire selection in setundef -init Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 121 ++++++++++++++++++++++++++++++---------- 1 file changed, 90 insertions(+), 31 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index e46d0a1dc..3eedc86b8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -393,53 +393,112 @@ struct SetundefPass : public Pass { ffbits.insert(bit); } - for (auto wire : module->wires()) + auto process_initwires = [&]() { - if (!wire->attributes.count("\\init")) - continue; + dict wire_weights; - for (auto bit : sigmap(wire)) - ffbits.erase(bit); + for (auto wire : initwires) + { + int weight = 0; - initwires.insert(wire); - } + for (auto bit : sigmap(wire)) + weight += ffbits.count(bit) ? +1 : -1; + + wire_weights[wire] = weight; + } + + initwires.sort([&](Wire *a, Wire *b) { return wire_weights.at(a) > wire_weights.at(b); }); + + for (auto wire : initwires) + { + Const &initval = wire->attributes["\\init"]; + initval.bits.resize(GetSize(wire), State::Sx); + + for (int i = 0; i < GetSize(wire); i++) { + SigBit bit = sigmap(SigBit(wire, i)); + if (initval[i] == State::Sx && ffbits.count(bit)) { + initval[i] = worker.next_bit(); + ffbits.erase(bit); + } + } + + if (initval.is_fully_undef()) + wire->attributes.erase("\\init"); + } + + initwires.clear(); + }; for (int wire_types = 0; wire_types < 2; wire_types++) { - pool ffbitsToErase; - for (auto wire : module->wires()) + // prioritize wires that already have an init attribute + if (!ffbits.empty()) { - if (wire->name[0] == (wire_types ? '\\' : '$')) { - next_wire: + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) + continue; + + if (!wire->attributes.count("\\init")) + continue; + + Const &initval = wire->attributes["\\init"]; + initval.bits.resize(GetSize(wire), State::Sx); + + if (initval.is_fully_undef()) { + wire->attributes.erase("\\init"); + continue; + } + + for (int i = 0; i < GetSize(wire); i++) + if (initval[i] != State::Sx) + ffbits.erase(sigmap(SigBit(wire, i))); + + initwires.insert(wire); + } + + process_initwires(); + } + + // next consider wires that completely contain bits to be initialized + if (!ffbits.empty()) + { + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) + continue; + + for (auto bit : sigmap(wire)) + if (!ffbits.count(bit)) + goto next_wire; + + initwires.insert(wire); + + next_wire: continue; } - for (auto bit : sigmap(wire)) - if (!ffbits.count(bit)) { - goto next_wire; - } + process_initwires(); + } - for (auto bit : sigmap(wire)) { - ffbitsToErase.insert(bit); + // finally use whatever wire we can find. + if (!ffbits.empty()) + { + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) + continue; + + for (auto bit : sigmap(wire)) + if (ffbits.count(bit)) + initwires.insert(wire); } - initwires.insert(wire); - } - for (const auto & bit : ffbitsToErase) { - ffbits.erase(bit); + process_initwires(); } } - for (auto wire : initwires) - { - Const &initval = wire->attributes["\\init"]; - - for (int i = 0; i < GetSize(wire); i++) - if (GetSize(initval) <= i) - initval.bits.push_back(worker.next_bit()); - else if (initval.bits[i] == State::Sx) - initval.bits[i] = worker.next_bit(); - } + log_assert(ffbits.empty()); } module->rewrite_sigspecs(worker);