mirror of https://github.com/YosysHQ/yosys.git
Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
This commit is contained in:
parent
c1abd3b02c
commit
bc8ab3ab44
|
@ -1350,7 +1350,7 @@ struct VerificSvaPP
|
|||
return default_net;
|
||||
}
|
||||
|
||||
if (inst->Type() == PRIM_SVA_AT) {
|
||||
if (inst->Type() == PRIM_SVA_AT || inst->Type() == PRIM_SVA_DISABLE_IFF) {
|
||||
Net *new_net = rewrite(get_ast_input2(inst));
|
||||
if (new_net) {
|
||||
inst->Disconnect(inst->View()->GetInput2());
|
||||
|
|
|
@ -0,0 +1,34 @@
|
|||
module top (
|
||||
input clk,
|
||||
input reset,
|
||||
input ping,
|
||||
input [1:0] cfg,
|
||||
output reg pong
|
||||
);
|
||||
reg [2:0] cnt;
|
||||
localparam integer maxdelay = 8;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
cnt <= 0;
|
||||
pong <= 0;
|
||||
end else begin
|
||||
cnt <= cnt - |cnt;
|
||||
pong <= cnt == 1;
|
||||
if (ping) cnt <= 4 + cfg;
|
||||
end
|
||||
end
|
||||
|
||||
assert property (
|
||||
@(posedge clk)
|
||||
disable iff (reset)
|
||||
not (ping ##1 !pong [*maxdelay])
|
||||
);
|
||||
|
||||
`ifndef FAIL
|
||||
assume property (
|
||||
@(posedge clk)
|
||||
not (cnt && ping)
|
||||
);
|
||||
`endif
|
||||
endmodule
|
Loading…
Reference in New Issue