mirror of https://github.com/YosysHQ/yosys.git
memory_dff: Remove code looking for $mux cells.
This job is now performed by `opt_dff`, which runs before this pass.
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d555454969
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bc717abad2
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@ -33,7 +33,6 @@ struct MemoryDffWorker
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vector<Cell*> dff_cells;
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vector<Cell*> dff_cells;
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dict<SigBit, SigBit> invbits;
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dict<SigBit, SigBit> invbits;
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dict<SigBit, int> sigbit_users_count;
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dict<SigBit, int> sigbit_users_count;
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dict<SigSpec, Cell*> mux_cells_a, mux_cells_b;
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pool<Cell*> forward_merged_dffs, candidate_dffs;
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pool<Cell*> forward_merged_dffs, candidate_dffs;
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FfInitVals initvals;
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FfInitVals initvals;
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@ -276,44 +275,6 @@ struct MemoryDffWorker
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if (sigbit_users_count[bit] > 1)
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if (sigbit_users_count[bit] > 1)
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goto skip_ff_after_read_merging;
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goto skip_ff_after_read_merging;
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if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
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{
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RTLIL::SigSpec en;
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std::vector<RTLIL::SigSpec> check_q;
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do {
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bool enable_invert = mux_cells_a.count(sig_data) != 0;
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Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
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check_q.push_back(sigmap(mux->getPort(enable_invert ? ID::B : ID::A)));
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sig_data = sigmap(mux->getPort(ID::Y));
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en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort(ID::S)) : mux->getPort(ID::S));
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} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
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for (auto bit : sig_data)
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if (sigbit_users_count[bit] > 1)
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goto skip_ff_after_read_merging;
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if (find_sig_after_dffe(sig_data, clk_data, clk_polarity, en_data, en_polarity) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) &&
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std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
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{
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if (en_data != State::S1 || !en_polarity) {
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if (!en_polarity)
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en_data = module->LogicNot(NEW_ID, en_data);
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en.append(en_data);
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}
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disconnect_dff(sig_data);
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cell->setPort(ID::CLK, clk_data);
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cell->setPort(ID::EN, en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en);
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cell->setPort(ID::DATA, sig_data);
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cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
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cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
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cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
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log("merged data $dff with rd enable to cell.\n");
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return;
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}
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}
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else
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{
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if (find_sig_after_dffe(sig_data, clk_data, clk_polarity, en_data, en_polarity) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
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if (find_sig_after_dffe(sig_data, clk_data, clk_polarity, en_data, en_polarity) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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{
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if (!en_polarity)
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if (!en_polarity)
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@ -328,7 +289,6 @@ struct MemoryDffWorker
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log("merged data $dff to cell.\n");
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log("merged data $dff to cell.\n");
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return;
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return;
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}
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}
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}
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skip_ff_after_read_merging:;
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skip_ff_after_read_merging:;
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RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
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RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
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@ -360,10 +320,6 @@ struct MemoryDffWorker
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for (auto cell : module->cells()) {
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)))
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if (cell->type.in(ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)))
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dff_cells.push_back(cell);
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dff_cells.push_back(cell);
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if (cell->type == ID($mux)) {
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mux_cells_a[sigmap(cell->getPort(ID::A))] = cell;
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mux_cells_b[sigmap(cell->getPort(ID::B))] = cell;
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}
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if (cell->type.in(ID($not), ID($_NOT_)) || (cell->type == ID($logic_not) && GetSize(cell->getPort(ID::A)) == 1)) {
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if (cell->type.in(ID($not), ID($_NOT_)) || (cell->type == ID($logic_not) && GetSize(cell->getPort(ID::A)) == 1)) {
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_y = cell->getPort(ID::Y);
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SigSpec sig_y = cell->getPort(ID::Y);
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