mirror of https://github.com/YosysHQ/yosys.git
kernel: fix DeleteWireWorker
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432a09af80
commit
bc51e609cb
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@ -1586,6 +1586,7 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
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const pool<RTLIL::Wire*> *wires_p;
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void operator()(RTLIL::SigSpec &sig) {
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sig.pack();
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for (auto &c : sig.chunks_)
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if (c.wire != NULL && wires_p->count(c.wire)) {
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c.wire = module->addWire(NEW_ID, c.width);
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@ -1599,16 +1600,10 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
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rhs.unpack();
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for (int i = 0; i < GetSize(lhs); i++) {
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RTLIL::SigBit &lhs_bit = lhs.bits_[i];
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if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) {
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lhs_bit.wire = module->addWire(NEW_ID);
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lhs_bit.offset = 0;
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continue;
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}
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RTLIL::SigBit &rhs_bit = rhs.bits_[i];
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if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire)) {
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rhs_bit.wire = module->addWire(NEW_ID);
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rhs_bit.offset = 0;
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continue;
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if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
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lhs_bit = State::Sx;
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rhs_bit = State::Sx;
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}
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}
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}
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