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stat: add tech tech-specific utilizations to json 

- refactor resource util. estimation/calculations for Xilinx and CMOS
 - don't print log_header if "-json" is set
This commit is contained in:
Kamyar Mohajerani 2022-09-13 17:07:19 -04:00 committed by Lofty
parent 50e267eace
commit bc1e579483
1 changed files with 91 additions and 65 deletions
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94
passes/cmds/stat.cc
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@ -149,32 +149,7 @@ struct statdata_t
} }
} }
void log_data(RTLIL::IdString mod_name, bool top_mod) unsigned int estimate_xilinx_lc()
{
log(" Number of wires: %6u\n", num_wires);
log(" Number of wire bits: %6u\n", num_wire_bits);
log(" Number of public wires: %6u\n", num_pub_wires);
log(" Number of public wire bits: %6u\n", num_pub_wire_bits);
log(" Number of memories: %6u\n", num_memories);
log(" Number of memory bits: %6u\n", num_memory_bits);
log(" Number of processes: %6u\n", num_processes);
log(" Number of cells: %6u\n", num_cells);
for (auto &it : num_cells_by_type)
if (it.second)
log(" %-26s %6u\n", log_id(it.first), it.second);
if (!unknown_cell_area.empty()) {
log("\n");
for (auto cell_type : unknown_cell_area)
log(" Area for cell type %s is unknown!\n", cell_type.c_str());
}
if (area != 0) {
log("\n");
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
}
if (tech == "xilinx")
{ {
unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)]; unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)];
unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)]; unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)];
@ -223,14 +198,12 @@ struct statdata_t
lc_cnt += (lut2_cnt + lut1_cnt + 1) / 2; lc_cnt += (lut2_cnt + lut1_cnt + 1) / 2;
log("\n"); return lc_cnt;
log(" Estimated number of LCs: %10u\n", lc_cnt);
} }
if (tech == "cmos") unsigned int cmos_transistor_count(bool *tran_cnt_exact)
{ {
unsigned int tran_cnt = 0; unsigned int tran_cnt = 0;
bool tran_cnt_exact = true;
auto &gate_costs = CellCosts::cmos_gate_cost(); auto &gate_costs = CellCosts::cmos_gate_cost();
for (auto it : num_cells_by_type) { for (auto it : num_cells_by_type) {
@ -242,9 +215,48 @@ struct statdata_t
else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_))) else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
tran_cnt += cnum * 16; tran_cnt += cnum * 16;
else else
tran_cnt_exact = false; *tran_cnt_exact = false;
} }
return tran_cnt;
}
void log_data(RTLIL::IdString mod_name, bool top_mod)
{
log(" Number of wires: %6u\n", num_wires);
log(" Number of wire bits: %6u\n", num_wire_bits);
log(" Number of public wires: %6u\n", num_pub_wires);
log(" Number of public wire bits: %6u\n", num_pub_wire_bits);
log(" Number of memories: %6u\n", num_memories);
log(" Number of memory bits: %6u\n", num_memory_bits);
log(" Number of processes: %6u\n", num_processes);
log(" Number of cells: %6u\n", num_cells);
for (auto &it : num_cells_by_type)
if (it.second)
log(" %-26s %6u\n", log_id(it.first), it.second);
if (!unknown_cell_area.empty()) {
log("\n");
for (auto cell_type : unknown_cell_area)
log(" Area for cell type %s is unknown!\n", cell_type.c_str());
}
if (area != 0) {
log("\n");
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
}
if (tech == "xilinx")
{
log("\n");
log(" Estimated number of LCs: %10u\n", estimate_xilinx_lc());
}
if (tech == "cmos")
{
bool tran_cnt_exact = true;
unsigned int tran_cnt = cmos_transistor_count(&tran_cnt_exact);
log("\n"); log("\n");
log(" Estimated number of transistors: %10u%s\n", tran_cnt, tran_cnt_exact ? "" : "+"); log(" Estimated number of transistors: %10u%s\n", tran_cnt, tran_cnt_exact ? "" : "+");
} }
@ -273,7 +285,20 @@ struct statdata_t
first_line = false; first_line = false;
} }
log("\n"); log("\n");
log(" }\n"); log(" }");
if (tech == "xilinx")
{
log(",\n");
log(" \"estimated_num_lc\": %10u", estimate_xilinx_lc());
}
if (tech == "cmos")
{
bool tran_cnt_exact = true;
unsigned int tran_cnt = cmos_transistor_count(&tran_cnt_exact);
log(",\n");
log(" \"estimated_num_transistors\": \"%10u%s\"", tran_cnt, tran_cnt_exact ? "" : "+");
}
log("\n");
log(" }"); log(" }");
} }
}; };
@ -352,8 +377,6 @@ struct StatPass : public Pass {
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
log_header(design, "Printing statistics.\n");
bool width_mode = false, json_mode = false; bool width_mode = false, json_mode = false;
RTLIL::Module *top_mod = nullptr; RTLIL::Module *top_mod = nullptr;
std::map<RTLIL::IdString, statdata_t> mod_stat; std::map<RTLIL::IdString, statdata_t> mod_stat;
@ -391,6 +414,9 @@ struct StatPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if(!json_mode)
log_header(design, "Printing statistics.\n");
if (techname != "" && techname != "xilinx" && techname != "cmos" && !json_mode) if (techname != "" && techname != "xilinx" && techname != "cmos" && !json_mode)
log_cmd_error("Unsupported technology: '%s'\n", techname.c_str()); log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());