From 45500f4dd9b0f423ccf4152a9d5017184047db1b Mon Sep 17 00:00:00 2001
From: Alain Dargelas <alain@silimate.com>
Date: Wed, 18 Dec 2024 21:48:33 -0800
Subject: [PATCH] A or B width extend

---
 passes/pmgen/peepopt_muxadd.pmg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/pmgen/peepopt_muxadd.pmg b/passes/pmgen/peepopt_muxadd.pmg
index 8b55f5c88..b15183854 100644
--- a/passes/pmgen/peepopt_muxadd.pmg
+++ b/passes/pmgen/peepopt_muxadd.pmg
@@ -24,8 +24,8 @@ endmatch
 
 code add_y add_a add_b add_a_ext
 	// Get adder signals
-	add_a_ext = SigSpec(add_a);
-	add_a_ext.extend_u0(GetSize(add_y), param(add, \A_SIGNED).as_bool());
+	add_a_ext = SigSpec(port(add, add_a_id));
+	add_a_ext.extend_u0(GetSize(add_y), add_a_signed.as_bool());
 	// Fanout of each adder Y bit should be 1 (no bit-split)
 	if (nusers(add_y) != 2)
 		reject;