mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'YosysHQ:main' into nix
This commit is contained in:
commit
badd803beb
|
@ -0,0 +1,55 @@
|
|||
name: Documentation Report
|
||||
description: Report a problem with the Yosys documentation
|
||||
labels: ["pending-verification"]
|
||||
body:
|
||||
- type: markdown
|
||||
attributes:
|
||||
value: >
|
||||
|
||||
If you have a general question, please ask it in the [Discussions](https://github.com/YosysHQ/yosys/discussions) area
|
||||
or join our [IRC Channel](https://web.libera.chat/#yosys) or [Community Slack](https://join.slack.com/t/yosyshq/shared_invite/zt-1aopkns2q-EiQ97BeQDt_pwvE41sGSuA).
|
||||
|
||||
|
||||
If you have found a bug in Yosys, or in building the documentation,
|
||||
please fill out the Bug Report issue form, this form is for problems
|
||||
with the live documentation on [Read the
|
||||
Docs](https://yosyshq.readthedocs.io/projects/yosys/). Please only
|
||||
report problems that appear on the latest version of the documentation.
|
||||
|
||||
|
||||
Please contact [YosysHQ GmbH](https://www.yosyshq.com/) if you need
|
||||
commercial support for Yosys.
|
||||
|
||||
- type: input
|
||||
id: docs_url
|
||||
attributes:
|
||||
label: Link to page
|
||||
description: "Please provide a link to the page where the problem was found."
|
||||
placeholder: "e.g. https://yosyshq.readthedocs.io/projects/yosys/"
|
||||
validations:
|
||||
required: true
|
||||
|
||||
- type: input
|
||||
id: build_number
|
||||
attributes:
|
||||
label: Build number
|
||||
description: "If possible, please provide the latest build number from https://readthedocs.org/projects/yosys/builds/."
|
||||
placeholder: "e.g. Build #24078236"
|
||||
validations:
|
||||
required: false
|
||||
|
||||
- type: textarea
|
||||
id: problem
|
||||
attributes:
|
||||
label: Issue
|
||||
description: "Please describe what is incorrect, invalid, or missing."
|
||||
validations:
|
||||
required: true
|
||||
|
||||
- type: textarea
|
||||
id: expected
|
||||
attributes:
|
||||
label: Expected
|
||||
description: "If applicable, please describe what should appear instead."
|
||||
validations:
|
||||
required: false
|
|
@ -0,0 +1,33 @@
|
|||
name: Build environment setup
|
||||
description: Configure build env for Yosys builds
|
||||
runs:
|
||||
using: composite
|
||||
steps:
|
||||
- name: Install Linux Dependencies
|
||||
if: runner.os == 'Linux'
|
||||
shell: bash
|
||||
run: |
|
||||
sudo apt-get update
|
||||
sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
|
||||
|
||||
- name: Install macOS Dependencies
|
||||
if: runner.os == 'macOS'
|
||||
shell: bash
|
||||
run: |
|
||||
HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf
|
||||
|
||||
- name: Linux runtime environment
|
||||
if: runner.os == 'Linux'
|
||||
shell: bash
|
||||
run: |
|
||||
echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
|
||||
echo "procs=$(nproc)" >> $GITHUB_ENV
|
||||
|
||||
- name: macOS runtime environment
|
||||
if: runner.os == 'macOS'
|
||||
shell: bash
|
||||
run: |
|
||||
echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH
|
||||
echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
|
||||
echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
|
||||
echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
|
|
@ -0,0 +1,181 @@
|
|||
name: Build and run tests
|
||||
|
||||
on: [push, pull_request]
|
||||
|
||||
jobs:
|
||||
pre_job:
|
||||
runs-on: ubuntu-latest
|
||||
outputs:
|
||||
should_skip: ${{ steps.skip_check.outputs.should_skip }}
|
||||
steps:
|
||||
- id: skip_check
|
||||
uses: fkirc/skip-duplicate-actions@v5
|
||||
with:
|
||||
paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
|
||||
# cancel previous builds if a new commit is pushed
|
||||
cancel_others: 'true'
|
||||
# only run on push *or* pull_request, not both
|
||||
concurrent_skipping: 'same_content_newer'
|
||||
pre_docs_job:
|
||||
runs-on: ubuntu-latest
|
||||
outputs:
|
||||
should_skip: ${{ steps.skip_check.outputs.should_skip }}
|
||||
steps:
|
||||
- id: skip_check
|
||||
uses: fkirc/skip-duplicate-actions@v5
|
||||
with:
|
||||
paths_ignore: '["**/README.md"]'
|
||||
# cancel previous builds if a new commit is pushed
|
||||
cancel_others: 'true'
|
||||
# only run on push *or* pull_request, not both
|
||||
concurrent_skipping: 'same_content_newer'
|
||||
|
||||
build-yosys:
|
||||
name: Reusable build
|
||||
runs-on: ${{ matrix.os }}
|
||||
needs: pre_docs_job
|
||||
if: needs.pre_docs_job.outputs.should_skip != 'true'
|
||||
env:
|
||||
CC: clang
|
||||
strategy:
|
||||
matrix:
|
||||
os: [ubuntu-latest, macos-latest]
|
||||
fail-fast: false
|
||||
steps:
|
||||
- name: Checkout Yosys
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: true
|
||||
|
||||
- name: Setup environment
|
||||
uses: ./.github/actions/setup-build-env
|
||||
|
||||
- name: Build
|
||||
shell: bash
|
||||
run: |
|
||||
mkdir build
|
||||
cd build
|
||||
make -f ../Makefile config-$CC
|
||||
make -f ../Makefile -j$procs
|
||||
|
||||
- name: Log yosys-config output
|
||||
run: |
|
||||
./yosys-config || true
|
||||
|
||||
- name: Compress build
|
||||
shell: bash
|
||||
run: |
|
||||
cd build
|
||||
tar -cvf ../build.tar share/ yosys yosys-*
|
||||
|
||||
- name: Store build artifact
|
||||
uses: actions/upload-artifact@v4
|
||||
with:
|
||||
name: build-${{ matrix.os }}
|
||||
path: build.tar
|
||||
retention-days: 1
|
||||
|
||||
test-yosys:
|
||||
name: Run tests
|
||||
runs-on: ${{ matrix.os }}
|
||||
needs: [build-yosys, pre_job]
|
||||
if: needs.pre_job.outputs.should_skip != 'true'
|
||||
env:
|
||||
CC: clang
|
||||
strategy:
|
||||
matrix:
|
||||
os: [ubuntu-latest, macos-latest]
|
||||
fail-fast: false
|
||||
steps:
|
||||
- name: Checkout Yosys
|
||||
uses: actions/checkout@v4
|
||||
|
||||
- name: Setup environment
|
||||
uses: ./.github/actions/setup-build-env
|
||||
|
||||
- name: Get iverilog
|
||||
shell: bash
|
||||
run: |
|
||||
git clone https://github.com/steveicarus/iverilog.git
|
||||
cd iverilog
|
||||
echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
|
||||
|
||||
- name: Cache iverilog
|
||||
id: cache-iverilog
|
||||
uses: actions/cache@v4
|
||||
with:
|
||||
path: .local/
|
||||
key: ${{ matrix.os }}-${{ env.IVERILOG_GIT }}
|
||||
|
||||
- name: Build iverilog
|
||||
if: steps.cache-iverilog.outputs.cache-hit != 'true'
|
||||
shell: bash
|
||||
run: |
|
||||
mkdir -p ${{ github.workspace }}/.local/
|
||||
cd iverilog
|
||||
autoconf
|
||||
CC=gcc CXX=g++ ./configure --prefix=${{ github.workspace }}/.local
|
||||
make -j$procs
|
||||
make install
|
||||
|
||||
- name: Download build artifact
|
||||
uses: actions/download-artifact@v4
|
||||
with:
|
||||
name: build-${{ matrix.os }}
|
||||
|
||||
- name: Uncompress build
|
||||
shell: bash
|
||||
run:
|
||||
tar -xvf build.tar
|
||||
|
||||
- name: Log yosys-config output
|
||||
run: |
|
||||
./yosys-config || true
|
||||
|
||||
- name: Run tests
|
||||
shell: bash
|
||||
run: |
|
||||
make -j$procs test TARGETS= EXTRA_TARGETS= CONFIG=$CC
|
||||
|
||||
- name: Report errors
|
||||
if: ${{ failure() }}
|
||||
shell: bash
|
||||
run: |
|
||||
find tests/**/*.err -print -exec cat {} \;
|
||||
|
||||
test-docs:
|
||||
name: Run docs tests
|
||||
runs-on: ${{ matrix.os }}
|
||||
needs: [build-yosys, pre_docs_job]
|
||||
if: needs.pre_docs_job.outputs.should_skip != 'true'
|
||||
env:
|
||||
CC: clang
|
||||
strategy:
|
||||
matrix:
|
||||
os: [ubuntu-latest]
|
||||
fail-fast: false
|
||||
steps:
|
||||
- name: Checkout Yosys
|
||||
uses: actions/checkout@v4
|
||||
|
||||
- name: Setup environment
|
||||
uses: ./.github/actions/setup-build-env
|
||||
|
||||
- name: Download build artifact
|
||||
uses: actions/download-artifact@v4
|
||||
with:
|
||||
name: build-${{ matrix.os }}
|
||||
|
||||
- name: Uncompress build
|
||||
shell: bash
|
||||
run:
|
||||
tar -xvf build.tar
|
||||
|
||||
- name: Log yosys-config output
|
||||
run: |
|
||||
./yosys-config || true
|
||||
|
||||
- name: Run tests
|
||||
shell: bash
|
||||
run: |
|
||||
make -C docs test -j${{ env.procs }}
|
|
@ -0,0 +1,79 @@
|
|||
name: Compiler testing
|
||||
|
||||
on: [push, pull_request]
|
||||
|
||||
jobs:
|
||||
pre_job:
|
||||
runs-on: ubuntu-latest
|
||||
outputs:
|
||||
should_skip: ${{ steps.skip_check.outputs.should_skip }}
|
||||
steps:
|
||||
- id: skip_check
|
||||
uses: fkirc/skip-duplicate-actions@v5
|
||||
with:
|
||||
paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
|
||||
# cancel previous builds if a new commit is pushed
|
||||
cancel_others: 'true'
|
||||
# only run on push *or* pull_request, not both
|
||||
concurrent_skipping: 'same_content_newer'
|
||||
|
||||
test-compile:
|
||||
runs-on: ${{ matrix.os }}
|
||||
needs: pre_job
|
||||
if: needs.pre_job.outputs.should_skip != 'true'
|
||||
env:
|
||||
CXXFLAGS: ${{ startsWith(matrix.compiler, 'gcc') && '-Wp,-D_GLIBCXX_ASSERTIONS' || ''}}
|
||||
CC_SHORT: ${{ startsWith(matrix.compiler, 'gcc') && 'gcc' || 'clang' }}
|
||||
strategy:
|
||||
matrix:
|
||||
os:
|
||||
- ubuntu-latest
|
||||
compiler:
|
||||
# oldest supported
|
||||
- 'clang-14'
|
||||
- 'gcc-10'
|
||||
# newest
|
||||
- 'clang'
|
||||
- 'gcc'
|
||||
include:
|
||||
# macOS
|
||||
- os: macos-13
|
||||
compiler: 'clang'
|
||||
# oldest clang not available on ubuntu-latest
|
||||
- os: ubuntu-22.04
|
||||
compiler: 'clang-11'
|
||||
fail-fast: false
|
||||
steps:
|
||||
- name: Checkout Yosys
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: true
|
||||
|
||||
- name: Setup environment
|
||||
uses: ./.github/actions/setup-build-env
|
||||
|
||||
- name: Setup Cpp
|
||||
uses: aminya/setup-cpp@v1
|
||||
with:
|
||||
compiler: ${{ matrix.compiler }}
|
||||
|
||||
- name: Tool versions
|
||||
shell: bash
|
||||
run: |
|
||||
$CC --version
|
||||
$CXX --version
|
||||
|
||||
# minimum standard
|
||||
- name: Build C++11
|
||||
shell: bash
|
||||
run: |
|
||||
make config-$CC_SHORT
|
||||
make -j$procs CXXSTD=c++11 compile-only
|
||||
|
||||
# maximum standard, only on newest compilers
|
||||
- name: Build C++20
|
||||
if: ${{ matrix.compiler == 'clang' || matrix.compiler == 'gcc'}}
|
||||
shell: bash
|
||||
run: |
|
||||
make config-$CC_SHORT
|
||||
make -j$procs CXXSTD=c++20 compile-only
|
|
@ -1,58 +0,0 @@
|
|||
name: Build and test doc code samples
|
||||
|
||||
on:
|
||||
pull_request:
|
||||
branches:
|
||||
- main
|
||||
|
||||
jobs:
|
||||
pre_job:
|
||||
runs-on: ubuntu-latest
|
||||
outputs:
|
||||
should_skip: ${{ steps.skip_check.outputs.should_skip }}
|
||||
steps:
|
||||
- id: skip_check
|
||||
uses: fkirc/skip-duplicate-actions@v5
|
||||
with:
|
||||
# cancel previous builds if a new commit is pushed
|
||||
cancel_others: 'true'
|
||||
# only run on push *or* pull_request, not both
|
||||
concurrent_skipping: 'same_content_newer'
|
||||
|
||||
test-docs:
|
||||
needs: pre_job
|
||||
if: needs.pre_job.outputs.should_skip != 'true'
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: Install Dependencies
|
||||
shell: bash
|
||||
run: |
|
||||
sudo apt-get update
|
||||
sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
|
||||
|
||||
- name: Setup GCC
|
||||
uses: Dup4/actions-setup-gcc@v1
|
||||
|
||||
- name: Runtime environment
|
||||
shell: bash
|
||||
env:
|
||||
WORKSPACE: ${{ github.workspace }}
|
||||
run: |
|
||||
echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
|
||||
echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
|
||||
echo "procs=$(nproc)" >> $GITHUB_ENV
|
||||
|
||||
- name: Checkout Yosys
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: true
|
||||
- name: Build yosys
|
||||
shell: bash
|
||||
run: |
|
||||
make config-gcc
|
||||
make -j${{ env.procs }}
|
||||
|
||||
- name: Run tests
|
||||
shell: bash
|
||||
run: |
|
||||
make -C docs test -j${{ env.procs }}
|
|
@ -1,147 +0,0 @@
|
|||
name: Build and run tests (Linux)
|
||||
|
||||
on: [push, pull_request]
|
||||
|
||||
jobs:
|
||||
pre_job:
|
||||
runs-on: ubuntu-latest
|
||||
outputs:
|
||||
should_skip: ${{ steps.skip_check.outputs.should_skip }}
|
||||
steps:
|
||||
- id: skip_check
|
||||
uses: fkirc/skip-duplicate-actions@v5
|
||||
with:
|
||||
paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
|
||||
# cancel previous builds if a new commit is pushed
|
||||
cancel_others: 'true'
|
||||
# only run on push *or* pull_request, not both
|
||||
concurrent_skipping: 'same_content_newer'
|
||||
|
||||
test-linux:
|
||||
needs: pre_job
|
||||
if: needs.pre_job.outputs.should_skip != 'true'
|
||||
runs-on: ${{ matrix.os.id }}
|
||||
strategy:
|
||||
matrix:
|
||||
os:
|
||||
- { id: ubuntu-20.04, name: focal }
|
||||
compiler:
|
||||
- 'clang-12'
|
||||
- 'gcc-11'
|
||||
cpp_std:
|
||||
- 'c++11'
|
||||
- 'c++14'
|
||||
- 'c++17'
|
||||
- 'c++20'
|
||||
include:
|
||||
# Limit the older compilers to C++11 mode
|
||||
- os: { id: ubuntu-20.04, name: focal }
|
||||
compiler: 'clang-11'
|
||||
cpp_std: 'c++11'
|
||||
- os: { id: ubuntu-20.04, name: focal }
|
||||
compiler: 'gcc-10'
|
||||
cpp_std: 'c++11'
|
||||
fail-fast: false
|
||||
steps:
|
||||
- name: Install Dependencies
|
||||
shell: bash
|
||||
run: |
|
||||
sudo apt-get update
|
||||
sudo apt-get install gperf build-essential bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
|
||||
|
||||
- name: Setup GCC
|
||||
if: startsWith(matrix.compiler, 'gcc')
|
||||
shell: bash
|
||||
run: |
|
||||
CXX=${CC/#gcc/g++}
|
||||
sudo apt-add-repository ppa:ubuntu-toolchain-r/test
|
||||
sudo apt-get update
|
||||
sudo apt-get install $CC $CXX
|
||||
echo "CC=$CC" >> $GITHUB_ENV
|
||||
echo "CXX=$CXX" >> $GITHUB_ENV
|
||||
echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV
|
||||
env:
|
||||
CC: ${{ matrix.compiler }}
|
||||
|
||||
- name: Setup Clang
|
||||
if: startsWith(matrix.compiler, 'clang')
|
||||
shell: bash
|
||||
run: |
|
||||
wget https://apt.llvm.org/llvm-snapshot.gpg.key
|
||||
sudo apt-key add llvm-snapshot.gpg.key
|
||||
rm llvm-snapshot.gpg.key
|
||||
sudo apt-add-repository "deb https://apt.llvm.org/${{ matrix.os.name }}/ llvm-toolchain-${{ matrix.os.name }} main"
|
||||
sudo apt-get update
|
||||
CXX=${CC/#clang/clang++}
|
||||
sudo apt-get install $CC $CXX
|
||||
echo "CC=$CC" >> $GITHUB_ENV
|
||||
echo "CXX=$CXX" >> $GITHUB_ENV
|
||||
env:
|
||||
CC: ${{ matrix.compiler }}
|
||||
|
||||
- name: Runtime environment
|
||||
shell: bash
|
||||
env:
|
||||
WORKSPACE: ${{ github.workspace }}
|
||||
run: |
|
||||
echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
|
||||
echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
|
||||
echo "procs=$(nproc)" >> $GITHUB_ENV
|
||||
|
||||
- name: Tool versions
|
||||
shell: bash
|
||||
run: |
|
||||
$CC --version
|
||||
$CXX --version
|
||||
|
||||
- name: Checkout Yosys
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: true
|
||||
- name: Get iverilog
|
||||
shell: bash
|
||||
run: |
|
||||
git clone https://github.com/steveicarus/iverilog.git
|
||||
cd iverilog
|
||||
echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
|
||||
|
||||
- name: Cache iverilog
|
||||
id: cache-iverilog
|
||||
uses: actions/cache@v4
|
||||
with:
|
||||
path: .local/
|
||||
key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
|
||||
|
||||
- name: Build iverilog
|
||||
if: steps.cache-iverilog.outputs.cache-hit != 'true'
|
||||
shell: bash
|
||||
run: |
|
||||
mkdir -p $GITHUB_WORKSPACE/.local/
|
||||
cd iverilog
|
||||
autoconf
|
||||
CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local
|
||||
make -j${{ env.procs }}
|
||||
make install
|
||||
|
||||
- name: Build yosys
|
||||
shell: bash
|
||||
run: |
|
||||
make config-${CC%%-*}
|
||||
make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
|
||||
|
||||
- name: Store build artifact
|
||||
if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
|
||||
uses: actions/upload-artifact@v4
|
||||
with:
|
||||
name: compiled-yosys
|
||||
path: yosys
|
||||
|
||||
- name: Run tests
|
||||
if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
|
||||
shell: bash
|
||||
run: |
|
||||
make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
|
||||
|
||||
- name: Log yosys-config output
|
||||
run: |
|
||||
./yosys-config || true
|
|
@ -1,92 +0,0 @@
|
|||
name: Build and run tests (macOS)
|
||||
|
||||
on: [push, pull_request]
|
||||
|
||||
jobs:
|
||||
pre_job:
|
||||
runs-on: ubuntu-latest
|
||||
outputs:
|
||||
should_skip: ${{ steps.skip_check.outputs.should_skip }}
|
||||
steps:
|
||||
- id: skip_check
|
||||
uses: fkirc/skip-duplicate-actions@v5
|
||||
with:
|
||||
paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
|
||||
# cancel previous builds if a new commit is pushed
|
||||
cancel_others: 'true'
|
||||
# only run on push *or* pull_request, not both
|
||||
concurrent_skipping: 'same_content_newer'
|
||||
|
||||
test-macos:
|
||||
needs: pre_job
|
||||
if: needs.pre_job.outputs.should_skip != 'true'
|
||||
runs-on: ${{ matrix.os.id }}
|
||||
strategy:
|
||||
matrix:
|
||||
os:
|
||||
- { id: macos-13, name: 'Ventura' }
|
||||
cpp_std:
|
||||
- 'c++11'
|
||||
- 'c++17'
|
||||
fail-fast: false
|
||||
steps:
|
||||
- name: Install Dependencies
|
||||
run: |
|
||||
HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash
|
||||
|
||||
- name: Runtime environment
|
||||
shell: bash
|
||||
env:
|
||||
WORKSPACE: ${{ github.workspace }}
|
||||
run: |
|
||||
echo "GITHUB_WORKSPACE=`pwd`" >> $GITHUB_ENV
|
||||
echo "$GITHUB_WORKSPACE/.local/bin" >> $GITHUB_PATH
|
||||
echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH
|
||||
echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH
|
||||
echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV
|
||||
|
||||
- name: Tool versions
|
||||
shell: bash
|
||||
run: |
|
||||
cc --version
|
||||
|
||||
- name: Checkout Yosys
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: true
|
||||
- name: Get iverilog
|
||||
shell: bash
|
||||
run: |
|
||||
git clone https://github.com/steveicarus/iverilog.git
|
||||
cd iverilog
|
||||
echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
|
||||
|
||||
- name: Cache iverilog
|
||||
id: cache-iverilog
|
||||
uses: actions/cache@v4
|
||||
with:
|
||||
path: .local/
|
||||
key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
|
||||
|
||||
- name: Build iverilog
|
||||
if: steps.cache-iverilog.outputs.cache-hit != 'true'
|
||||
shell: bash
|
||||
run: |
|
||||
mkdir -p $GITHUB_WORKSPACE/.local/
|
||||
cd iverilog
|
||||
autoconf
|
||||
CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local/
|
||||
make -j${{ env.procs }}
|
||||
make install
|
||||
|
||||
- name: Build yosys
|
||||
shell: bash
|
||||
run: |
|
||||
make config-clang
|
||||
make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc
|
||||
|
||||
- name: Run tests
|
||||
if: matrix.cpp_std == 'c++11'
|
||||
shell: bash
|
||||
run: |
|
||||
make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc
|
|
@ -45,4 +45,3 @@ __pycache__
|
|||
/tests/unit/bintest/
|
||||
/tests/unit/objtest/
|
||||
/tests/ystests
|
||||
/build
|
||||
|
|
71
Makefile
71
Makefile
|
@ -3,7 +3,6 @@ CONFIG := none
|
|||
# CONFIG := clang
|
||||
# CONFIG := gcc
|
||||
# CONFIG := afl-gcc
|
||||
# CONFIG := emcc
|
||||
# CONFIG := wasi
|
||||
# CONFIG := mxe
|
||||
# CONFIG := msys2-32
|
||||
|
@ -142,7 +141,7 @@ LIBS += -lrt
|
|||
endif
|
||||
endif
|
||||
|
||||
YOSYS_VER := 0.41+8
|
||||
YOSYS_VER := 0.41+83
|
||||
|
||||
# Note: We arrange for .gitcommit to contain the (short) commit hash in
|
||||
# tarballs generated with git-archive(1) using .gitattributes. The git repo
|
||||
|
@ -254,45 +253,6 @@ CXX = g++
|
|||
CXXFLAGS += -std=gnu++11 -Os
|
||||
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
|
||||
|
||||
else ifeq ($(CONFIG),emcc)
|
||||
CXX = emcc
|
||||
CXXFLAGS := -std=$(CXXSTD) $(filter-out -fPIC -ggdb,$(CXXFLAGS))
|
||||
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DABC_MEMALIGN=8"
|
||||
EMCC_CXXFLAGS := -Os -Wno-warn-absolute-paths
|
||||
EMCC_LINKFLAGS := --embed-file share
|
||||
EMCC_LINKFLAGS += -s NO_EXIT_RUNTIME=1
|
||||
EMCC_LINKFLAGS += -s EXPORTED_FUNCTIONS="['_main','_run','_prompt','_errmsg','_memset']"
|
||||
EMCC_LINKFLAGS += -s TOTAL_MEMORY=134217728
|
||||
EMCC_LINKFLAGS += -s EXPORTED_RUNTIME_METHODS='["ccall", "cwrap"]'
|
||||
# https://github.com/kripken/emscripten/blob/master/src/settings.js
|
||||
CXXFLAGS += $(EMCC_CXXFLAGS)
|
||||
LINKFLAGS += $(EMCC_LINKFLAGS)
|
||||
LIBS =
|
||||
EXE = .js
|
||||
|
||||
DISABLE_SPAWN := 1
|
||||
|
||||
TARGETS := $(filter-out $(PROGRAM_PREFIX)yosys-config,$(TARGETS))
|
||||
EXTRA_TARGETS += yosysjs-$(YOSYS_VER).zip
|
||||
|
||||
ifeq ($(ENABLE_ABC),1)
|
||||
LINK_ABC := 1
|
||||
DISABLE_ABC_THREADS := 1
|
||||
endif
|
||||
|
||||
viz.js:
|
||||
wget -O viz.js.part https://github.com/mdaines/viz.js/releases/download/0.0.3/viz.js
|
||||
mv viz.js.part viz.js
|
||||
|
||||
yosysjs-$(YOSYS_VER).zip: yosys.js viz.js misc/yosysjs/*
|
||||
rm -rf yosysjs-$(YOSYS_VER) yosysjs-$(YOSYS_VER).zip
|
||||
mkdir -p yosysjs-$(YOSYS_VER)
|
||||
cp viz.js misc/yosysjs/* yosys.js yosys.wasm yosysjs-$(YOSYS_VER)/
|
||||
zip -r yosysjs-$(YOSYS_VER).zip yosysjs-$(YOSYS_VER)
|
||||
|
||||
yosys.html: misc/yosys.html
|
||||
$(P) cp misc/yosys.html yosys.html
|
||||
|
||||
else ifeq ($(CONFIG),wasi)
|
||||
ifeq ($(WASI_SDK),)
|
||||
CXX = clang++
|
||||
|
@ -357,7 +317,7 @@ CXXFLAGS += -std=$(CXXSTD) -Os
|
|||
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H $(ABC_ARCHFLAGS)"
|
||||
|
||||
else
|
||||
$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, emcc, mxe, msys2-32, msys2-64, none)
|
||||
$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, mxe, msys2-32, msys2-64, none)
|
||||
endif
|
||||
|
||||
ifeq ($(ENABLE_LIBYOSYS),1)
|
||||
|
@ -495,7 +455,7 @@ LIBS += -lpthread
|
|||
endif
|
||||
else
|
||||
ifeq ($(ABCEXTERNAL),)
|
||||
TARGETS += $(PROGRAM_PREFIX)yosys-abc$(EXE)
|
||||
TARGETS := $(PROGRAM_PREFIX)yosys-abc$(EXE) $(TARGETS)
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
@ -727,9 +687,11 @@ top-all: $(TARGETS) $(EXTRA_TARGETS)
|
|||
@echo " Build successful."
|
||||
@echo ""
|
||||
|
||||
ifeq ($(CONFIG),emcc)
|
||||
yosys.js: $(filter-out yosysjs-$(YOSYS_VER).zip,$(EXTRA_TARGETS))
|
||||
endif
|
||||
.PHONY: compile-only
|
||||
compile-only: $(OBJS) $(GENFILES) $(EXTRA_TARGETS)
|
||||
@echo ""
|
||||
@echo " Compile successful."
|
||||
@echo ""
|
||||
|
||||
$(PROGRAM_PREFIX)yosys$(EXE): $(OBJS)
|
||||
$(P) $(CXX) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LINKFLAGS) $(LINKFLAGS) $(OBJS) $(LIBS) $(LIBS_VERIFIC)
|
||||
|
@ -788,7 +750,6 @@ check-git-abc:
|
|||
echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
|
||||
exit 1; \
|
||||
elif git -C "$(YOSYS_SRC)" submodule status abc 2>/dev/null | grep -q '^ '; then \
|
||||
echo "'abc' is a git submodule. Continuing."; \
|
||||
exit 0; \
|
||||
elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
|
||||
echo "'abc' comes from a tarball. Continuing."; \
|
||||
|
@ -806,9 +767,7 @@ check-git-abc:
|
|||
exit 1; \
|
||||
fi
|
||||
|
||||
ABC_SOURCES := $(wildcard $(YOSYS_SRC)/abc/*)
|
||||
|
||||
abc/abc$(EXE) abc/libabc.a: $(ABC_SOURCES) check-git-abc
|
||||
abc/abc$(EXE) abc/libabc.a: check-git-abc
|
||||
$(P)
|
||||
$(Q) mkdir -p abc && $(MAKE) -C $(PROGRAM_PREFIX)abc -f "$(realpath $(YOSYS_SRC)/abc/Makefile)" ABCSRC="$(realpath $(YOSYS_SRC)/abc/)" $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc",PROG="abc$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc.a)
|
||||
|
||||
|
@ -1022,7 +981,9 @@ clean:
|
|||
rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_*
|
||||
rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff
|
||||
rm -f tests/tools/cmp_tbdata
|
||||
$(MAKE) -C docs clean
|
||||
-$(MAKE) -C docs clean
|
||||
-$(MAKE) -C docs/images clean
|
||||
rm -rf docs/source/cmd docs/util/__pycache__
|
||||
|
||||
clean-abc:
|
||||
$(MAKE) -C abc DEP= clean
|
||||
|
@ -1085,14 +1046,6 @@ config-gcc-static: clean
|
|||
config-afl-gcc: clean
|
||||
echo 'CONFIG := afl-gcc' > Makefile.conf
|
||||
|
||||
config-emcc: clean
|
||||
echo 'CONFIG := emcc' > Makefile.conf
|
||||
echo 'ENABLE_TCL := 0' >> Makefile.conf
|
||||
echo 'ENABLE_ABC := 0' >> Makefile.conf
|
||||
echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
|
||||
echo 'ENABLE_READLINE := 0' >> Makefile.conf
|
||||
echo 'ENABLE_ZLIB := 0' >> Makefile.conf
|
||||
|
||||
config-wasi: clean
|
||||
echo 'CONFIG := wasi' > Makefile.conf
|
||||
echo 'ENABLE_TCL := 0' >> Makefile.conf
|
||||
|
|
|
@ -24,3 +24,17 @@ a.external {
|
|||
th {
|
||||
text-align: left;
|
||||
}
|
||||
|
||||
body[data-theme="dark"] {
|
||||
.invert-helper {
|
||||
filter: url("data:image/svg+xml,<svg xmlns='http%3A//www.w3.org/2000/svg'><filter id='f'><feColorMatrix color-interpolation-filters='sRGB' type='matrix' values='1.47 -1.73 -0.467 0 0.867 -0.733 0.467 -0.467 0 0.867 -0.667 -1.07 1.07 0 0.867 0 0 0 1.0 0'></feColorMatrix></filter></svg>#f");
|
||||
}
|
||||
}
|
||||
|
||||
@media (prefers-color-scheme: dark) {
|
||||
body:not([data-theme="light"]) {
|
||||
.invert-helper {
|
||||
filter: url("data:image/svg+xml,<svg xmlns='http%3A//www.w3.org/2000/svg'><filter id='f'><feColorMatrix color-interpolation-filters='sRGB' type='matrix' values='1.47 -1.73 -0.467 0 0.867 -0.733 0.467 -0.467 0 0.867 -0.667 -1.07 1.07 0 0.867 0 0 0 1.0 0'></feColorMatrix></filter></svg>#f");
|
||||
}
|
||||
}
|
||||
}
|
|
@ -24,7 +24,7 @@ circuit to a functionally equivalent low-level representation of a circuit.
|
|||
abstraction and how they relate to different kinds of synthesis.
|
||||
|
||||
.. figure:: /_images/primer/basics_abstractions.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:Basics_abstractions
|
||||
|
||||
Different levels of abstraction and synthesis.
|
||||
|
@ -499,7 +499,7 @@ using a series of tools and the results are again verified using simulation.
|
|||
This process is illustrated in :numref:`Fig. %s <fig:Basics_flow>`.
|
||||
|
||||
.. figure:: /_images/primer/basics_flow.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:Basics_flow
|
||||
|
||||
Typical design flow. Green boxes represent manually created models.
|
||||
|
@ -598,7 +598,7 @@ Let's consider the following BNF (in Bison syntax):
|
|||
expr: TOK_IDENTIFIER | TOK_NUMBER | expr TOK_PLUS expr;
|
||||
|
||||
.. figure:: /_images/primer/basics_parsetree.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:Basics_parsetree
|
||||
|
||||
Example parse tree for the Verilog expression
|
||||
|
@ -627,7 +627,7 @@ suitable for further processing. In compilers this is often an assembler-like
|
|||
three-address-code intermediate representation. :cite:p:`Dragonbook`
|
||||
|
||||
.. figure:: /_images/primer/basics_ast.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:Basics_ast
|
||||
|
||||
Example abstract syntax tree for the Verilog expression
|
||||
|
|
|
@ -122,7 +122,7 @@ Since we're just getting started, let's instead begin with :yoscrypt:`hierarchy
|
|||
Our ``addr_gen`` circuit now looks like this:
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/addr_gen_hier.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: addr_gen_hier
|
||||
|
||||
``addr_gen`` module after :cmd:ref:`hierarchy`
|
||||
|
@ -145,7 +145,7 @@ we run it. For now, we will call :yoscrypt:`proc -noopt` to prevent some
|
|||
automatic optimizations which would normally happen.
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/addr_gen_proc.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: addr_gen_proc
|
||||
|
||||
``addr_gen`` module after :yoscrypt:`proc -noopt`
|
||||
|
@ -166,7 +166,7 @@ the same time by separating them with a colon and space: :yoscrypt:`opt_expr;
|
|||
clean`.
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/addr_gen_clean.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: addr_gen_clean
|
||||
|
||||
``addr_gen`` module after :yoscrypt:`opt_expr; clean`
|
||||
|
@ -252,7 +252,7 @@ command only works with a single module, so you may need to call it with
|
|||
:doc:`/getting_started/scripting_intro` has more on how to use :cmd:ref:`show`.
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_proc.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_proc
|
||||
|
||||
``rdata`` output after :cmd:ref:`proc`
|
||||
|
@ -298,7 +298,7 @@ optimizations between modules which would otherwise be missed. Let's run
|
|||
:caption: output of :yoscrypt:`flatten;;`
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_flat.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_flat
|
||||
|
||||
``rdata`` output after :yoscrypt:`flatten;;`
|
||||
|
@ -385,7 +385,7 @@ options is able to fold one of the ``$mux`` cells into the ``$adff`` to form an
|
|||
:caption: output of :cmd:ref:`opt_dff`
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_adffe.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_adffe
|
||||
|
||||
``rdata`` output after :cmd:ref:`opt_dff`
|
||||
|
@ -424,7 +424,7 @@ the schematic and see the output of that cell has now changed.
|
|||
.. todo:: pending bugfix in :cmd:ref:`wreduce` and/or :cmd:ref:`opt_clean`
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_wreduce.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_wreduce
|
||||
|
||||
``rdata`` output after :cmd:ref:`wreduce`
|
||||
|
@ -446,7 +446,7 @@ Our next command to run is
|
|||
:caption: output of :cmd:ref:`memory_dff`
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_memrdv2.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_memrdv2
|
||||
|
||||
``rdata`` output after :cmd:ref:`memory_dff`
|
||||
|
@ -535,7 +535,7 @@ example design:
|
|||
:caption: output of :cmd:ref:`alumacc`
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_alumacc.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_alumacc
|
||||
|
||||
``rdata`` output after :cmd:ref:`alumacc`
|
||||
|
@ -553,7 +553,7 @@ operating on the same memory only in the abstract. :cmd:ref:`memory_collect`
|
|||
combines all of the reads and writes for a memory block into a single cell.
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_coarse.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_coarse
|
||||
|
||||
``rdata`` output after :cmd:ref:`memory_collect`
|
||||
|
@ -604,7 +604,7 @@ Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap` and
|
|||
:caption: ``map_ram`` section
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_map_ram.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_map_ram
|
||||
|
||||
``rdata`` output after :ref:`map_ram`
|
||||
|
@ -646,7 +646,7 @@ into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`.
|
|||
:caption: ``map_ffram`` section
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_map_ffram.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_map_ffram
|
||||
|
||||
``rdata`` output after :ref:`map_ffram`
|
||||
|
@ -682,7 +682,7 @@ replaced with single-bit ``$_MUX_`` and ``$_DFFE_PP0P_`` cells, while the
|
|||
:caption: ``map_gates`` section
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_map_gates.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_map_gates
|
||||
|
||||
``rdata`` output after :ref:`map_gates`
|
||||
|
@ -711,7 +711,7 @@ instead with an ``$_AND_`` cell.
|
|||
:caption: ``map_ffs`` section
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_map_ffs.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_map_ffs
|
||||
|
||||
``rdata`` output after :ref:`map_ffs`
|
||||
|
@ -737,7 +737,7 @@ what the difference between these two commands are, refer to
|
|||
:caption: ``map_luts`` section
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_map_luts.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_map_luts
|
||||
|
||||
``rdata`` output after :ref:`map_luts`
|
||||
|
@ -754,7 +754,7 @@ Finally we use :cmd:ref:`techmap` to map the generic ``$lut`` cells to iCE40
|
|||
:caption: ``map_cells`` section
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_map_cells.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: rdata_map_cells
|
||||
|
||||
``rdata`` output after :ref:`map_cells`
|
||||
|
|
|
@ -108,7 +108,7 @@ what the different symbols represent, see :ref:`interactive_show` and the
|
|||
:doc:`/using_yosys/more_scripting/interactive_investigation` page.
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/addr_gen_show.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: addr_gen_show
|
||||
|
||||
Calling :yoscrypt:`show addr_gen` after :cmd:ref:`hierarchy`
|
||||
|
@ -158,7 +158,7 @@ selection<select_new_cells>` and called it ``new_cells``? We saw in the
|
|||
``$eq``. We can call :cmd:ref:`show` on that selection just as easily:
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/new_cells_show.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: new_cells_show
|
||||
|
||||
Calling :yoscrypt:`show -notitle @new_cells`
|
||||
|
@ -173,7 +173,7 @@ the two ``PROC`` blocks. To achieve this highlight, we make use of the
|
|||
:yoscrypt:`-color` option:
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/addr_gen_hier.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Calling :yoscrypt:`show -color maroon3 @new_cells -color cornflowerblue p:* -notitle`
|
||||
|
||||
|
|
|
@ -151,7 +151,7 @@ extensible and therefore is a good basis for implementing custom synthesis tools
|
|||
for specialised tasks.
|
||||
|
||||
.. figure:: /_images/primer/levels_of_abstraction.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:Levels_of_abstraction
|
||||
|
||||
Where Yosys exists in the layers of abstraction
|
||||
|
|
|
@ -56,7 +56,7 @@ is shown.
|
|||
``xdot example_first.dot`` etc.
|
||||
|
||||
.. figure:: /_images/code_examples/show/example_first.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Output of the first :cmd:ref:`show` command in :numref:`example_ys`
|
||||
|
||||
|
@ -88,7 +88,7 @@ The :cmd:ref:`proc` command transforms the process from the first diagram into a
|
|||
multiplexer and a d-type flip-flop, which brings us to the second diagram:
|
||||
|
||||
.. figure:: /_images/code_examples/show/example_second.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Output of the second :cmd:ref:`show` command in :numref:`example_ys`
|
||||
|
||||
|
@ -110,7 +110,7 @@ In this script we directly call :cmd:ref:`opt` as the next step, which finally
|
|||
leads us to the third diagram:
|
||||
|
||||
.. figure:: /_images/code_examples/show/example_third.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: example_out
|
||||
|
||||
Output of the third :cmd:ref:`show` command in :ref:`example_ys`
|
||||
|
@ -137,7 +137,7 @@ that operate on wide integers, it also introduces some additional complexity
|
|||
when the individual bits of of a signal vector are accessed.
|
||||
|
||||
.. figure:: /_images/code_examples/show/splice.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: splice_dia
|
||||
|
||||
Output of ``yosys -p 'prep -top splice_demo; show' splice.v``
|
||||
|
@ -165,7 +165,7 @@ Gate level netlists
|
|||
mapped to a cell library:
|
||||
|
||||
.. figure:: /_images/code_examples/show/cmos_00.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: first_pitfall
|
||||
|
||||
A half-adder built from simple CMOS gates, demonstrating common pitfalls when
|
||||
|
@ -185,7 +185,7 @@ column. Secondly the two-bit vector ``y`` requires breakout-boxes for its
|
|||
individual bits, resulting in an unnecessary complex diagram.
|
||||
|
||||
.. figure:: /_images/code_examples/show/cmos_01.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: second_pitfall
|
||||
|
||||
Effects of :cmd:ref:`splitnets` command and of providing a cell library on
|
||||
|
@ -358,10 +358,10 @@ reorganizing a module in Yosys and checking the resulting circuit.
|
|||
:end-before: cd ..
|
||||
|
||||
.. figure:: /_images/code_examples/scrambler/scrambler_p01.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. figure:: /_images/code_examples/scrambler/scrambler_p02.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Analyzing the resulting circuit with :doc:`/cmd/eval`:
|
||||
|
||||
|
@ -442,7 +442,7 @@ if the circuit under investigation is encapsulated in a separate module.
|
|||
Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
|
||||
|
||||
.. figure:: /_images/code_examples/selections/memdemo_00.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
``memdemo``
|
||||
|
||||
|
@ -463,18 +463,18 @@ name of the new cell in the current module. The resulting circuits are shown
|
|||
below.
|
||||
|
||||
.. figure:: /_images/code_examples/selections/submod_02.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
``outstage``
|
||||
|
||||
.. figure:: /_images/code_examples/selections/submod_03.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: selstage
|
||||
|
||||
``selstage``
|
||||
|
||||
.. figure:: /_images/code_examples/selections/submod_01.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
``scramble``
|
||||
|
||||
|
|
|
@ -160,7 +160,7 @@ Selecting ``a:sumstuff`` in this module will yield the following circuit
|
|||
diagram:
|
||||
|
||||
.. figure:: /_images/code_examples/selections/sumprod_00.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: sumprod_00
|
||||
|
||||
Output of ``show a:sumstuff`` on :numref:`sumprod`
|
||||
|
@ -177,7 +177,7 @@ selected wire it selects all cells connected to the wire and vice versa. So
|
|||
:yoscrypt:`show a:sumstuff %x` yields the diagram shown in :numref:`sumprod_01`:
|
||||
|
||||
.. figure:: /_images/code_examples/selections/sumprod_01.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: sumprod_01
|
||||
|
||||
Output of ``show a:sumstuff %x`` on :numref:`sumprod`
|
||||
|
@ -200,22 +200,22 @@ input ports.
|
|||
The following sequence of diagrams demonstrates this step-wise expansion:
|
||||
|
||||
.. figure:: /_images/code_examples/selections/sumprod_02.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Output of :yoscrypt:`show prod` on :numref:`sumprod`
|
||||
|
||||
.. figure:: /_images/code_examples/selections/sumprod_03.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Output of :yoscrypt:`show prod %ci` on :numref:`sumprod`
|
||||
|
||||
.. figure:: /_images/code_examples/selections/sumprod_04.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Output of :yoscrypt:`show prod %ci %ci` on :numref:`sumprod`
|
||||
|
||||
.. figure:: /_images/code_examples/selections/sumprod_05.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Output of :yoscrypt:`show prod %ci %ci %ci` on :numref:`sumprod`
|
||||
|
||||
|
@ -280,7 +280,7 @@ provided :file:`memdemo.v` is in the same directory. We can now change to the
|
|||
diagram in :numref:`memdemo_00`.
|
||||
|
||||
.. figure:: /_images/code_examples/selections/memdemo_00.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: memdemo_00
|
||||
|
||||
Complete circuit diagram for the design shown in :numref:`memdemo_src`
|
||||
|
@ -291,7 +291,7 @@ output signal, ``y``, and its immediate predecessors. Remember `Selecting logic
|
|||
cones`_ from above, we can use :yoscrypt:`show y %ci2`:
|
||||
|
||||
.. figure:: /_images/code_examples/selections/memdemo_01.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: memdemo_01
|
||||
|
||||
Output of :yoscrypt:`show y %ci2`
|
||||
|
@ -303,7 +303,7 @@ wire into the input ``D`` of the flip-flop cell (indicated by the ``$`` at the
|
|||
start of the name). Let's go a bit further now and try :yoscrypt:`show y %ci5`:
|
||||
|
||||
.. figure:: /_images/code_examples/selections/memdemo_02.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: memdemo_02
|
||||
|
||||
Output of :yoscrypt:`show y %ci5`
|
||||
|
@ -317,7 +317,7 @@ brackets. In this case, we want to exclude the ``S`` port of the ``$mux`` cell
|
|||
type with :yoscrypt:`show y %ci5:-$mux[S]`:
|
||||
|
||||
.. figure:: /_images/code_examples/selections/memdemo_03.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: memdemo_03
|
||||
|
||||
Output of :yoscrypt:`show y %ci5:-$mux[S]`
|
||||
|
@ -328,7 +328,7 @@ flip-flop and the 2nd action selects the entire input cone without going over
|
|||
multiplexer select inputs and flip-flop cells:
|
||||
|
||||
.. figure:: /_images/code_examples/selections/memdemo_05.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: memdemo_05
|
||||
|
||||
Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``
|
||||
|
@ -340,7 +340,7 @@ ignoring any ports named ``CLK`` or ``S``:
|
|||
.. TODO:: pending discussion on whether rule ordering is a bug or a feature
|
||||
|
||||
.. figure:: /_images/code_examples/selections/memdemo_04.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: memdemo_04
|
||||
|
||||
Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux`
|
||||
|
@ -417,6 +417,6 @@ Example code from |code_examples/selections|_:
|
|||
:name: select_ys
|
||||
|
||||
.. figure:: /_images/code_examples/selections/select.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Circuit diagram produced by :numref:`select_ys`
|
||||
|
|
|
@ -51,7 +51,7 @@ Loading the design
|
|||
Our circuit now looks like this:
|
||||
|
||||
.. figure:: /_images/code_examples/intro/counter_00.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: counter-hierarchy
|
||||
|
||||
``counter`` after :cmd:ref:`hierarchy`
|
||||
|
@ -66,7 +66,7 @@ Coarse-grain representation
|
|||
:caption: :file:`counter.ys` - the high-level stuff
|
||||
|
||||
.. figure:: /_images/code_examples/intro/counter_01.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Coarse-grain representation of the ``counter`` module
|
||||
|
||||
|
@ -80,7 +80,7 @@ Logic gate mapping
|
|||
:caption: :file:`counter.ys` - mapping to internal cell library
|
||||
|
||||
.. figure:: /_images/code_examples/intro/counter_02.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
``counter`` after :cmd:ref:`techmap`
|
||||
|
||||
|
@ -111,7 +111,7 @@ Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
|
|||
The final version of our ``counter`` module looks like this:
|
||||
|
||||
.. figure:: /_images/code_examples/intro/counter_03.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
``counter`` after hardware cell mapping
|
||||
|
||||
|
|
|
@ -23,7 +23,7 @@ Example code can be found in |code_examples/macc|_.
|
|||
:lines: 1-2
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
before :cmd:ref:`extract`
|
||||
|
||||
|
@ -32,7 +32,7 @@ Example code can be found in |code_examples/macc|_.
|
|||
:lines: 6
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
after :cmd:ref:`extract`
|
||||
|
||||
|
@ -49,20 +49,20 @@ Example code can be found in |code_examples/macc|_.
|
|||
:caption: :file:`macc_simple_test_01.v`
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_simple_test_01a.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_simple_test_01b.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/macc/macc_simple_test_02.v
|
||||
:language: verilog
|
||||
:caption: :file:`macc_simple_test_02.v`
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_simple_test_02a.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_simple_test_02b.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
The wrap-extract-unwrap method
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
@ -149,10 +149,10 @@ Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
|
|||
:caption: ``test1`` of :file:`macc_xilinx_test.v`
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test1a.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
|
||||
:language: verilog
|
||||
|
@ -160,15 +160,15 @@ Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
|
|||
:caption: ``test2`` of :file:`macc_xilinx_test.v`
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test2a.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Wrapping in ``test1``:
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
|
||||
:language: yoscrypt
|
||||
|
@ -176,12 +176,12 @@ Wrapping in ``test1``:
|
|||
:end-before: end part c
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Wrapping in ``test2``:
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
|
||||
:language: yoscrypt
|
||||
|
@ -189,12 +189,12 @@ Wrapping in ``test2``:
|
|||
:end-before: end part c
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Extract in ``test1``:
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
|
||||
:language: yoscrypt
|
||||
|
@ -202,12 +202,12 @@ Extract in ``test1``:
|
|||
:end-before: end part d
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test1d.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Extract in ``test2``:
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
|
||||
:language: yoscrypt
|
||||
|
@ -215,12 +215,12 @@ Extract in ``test2``:
|
|||
:end-before: end part d
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Unwrap in ``test2``:
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
|
||||
:language: yoscrypt
|
||||
|
@ -228,4 +228,4 @@ Unwrap in ``test2``:
|
|||
:end-before: end part e
|
||||
|
||||
.. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
|
@ -39,7 +39,7 @@ Example
|
|||
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
|
||||
|
||||
.. figure:: /_images/code_examples/synth_flow/memory_01.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/synth_flow/memory_01.ys
|
||||
:language: yoscrypt
|
||||
|
@ -50,7 +50,7 @@ Example
|
|||
:caption: :file:`memory_01.v`
|
||||
|
||||
.. figure:: /_images/code_examples/synth_flow/memory_02.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/synth_flow/memory_02.v
|
||||
:language: verilog
|
||||
|
|
|
@ -88,7 +88,7 @@ trees can interfere with other optimizations.
|
|||
:caption: example verilog for demonstrating :cmd:ref:`opt_expr`
|
||||
|
||||
.. figure:: /_images/code_examples/opt/opt_expr.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Before and after :cmd:ref:`opt_expr`
|
||||
|
||||
|
@ -111,7 +111,7 @@ possible optimizations.
|
|||
:caption: example verilog for demonstrating :cmd:ref:`opt_merge`
|
||||
|
||||
.. figure:: /_images/code_examples/opt/opt_merge.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Before and after :cmd:ref:`opt_merge`
|
||||
|
||||
|
@ -133,7 +133,7 @@ detects this contradiction and replaces the inner multiplexer with a constant 1,
|
|||
yielding the logic for ``y = a ? b : d``.
|
||||
|
||||
.. figure:: /_images/code_examples/opt/opt_muxtree.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Before and after :cmd:ref:`opt_muxtree`
|
||||
|
||||
|
@ -172,7 +172,7 @@ multiplexing its output to multiplexing the non-shared input signals.
|
|||
:caption: example verilog for demonstrating :cmd:ref:`opt_share`
|
||||
|
||||
.. figure:: /_images/code_examples/opt/opt_share.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Before and after :cmd:ref:`opt_share`
|
||||
|
||||
|
|
|
@ -42,10 +42,10 @@ Example
|
|||
:caption: :file:`proc_01.ys`
|
||||
|
||||
.. figure:: /_images/code_examples/synth_flow/proc_01.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. figure:: /_images/code_examples/synth_flow/proc_02.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/synth_flow/proc_02.v
|
||||
:language: verilog
|
||||
|
@ -56,7 +56,7 @@ Example
|
|||
:caption: :file:`proc_02.ys`
|
||||
|
||||
.. figure:: /_images/code_examples/synth_flow/proc_03.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/synth_flow/proc_03.ys
|
||||
:language: yoscrypt
|
||||
|
|
|
@ -38,7 +38,7 @@ This document will focus on the much simpler version of RTLIL left after the
|
|||
commands :cmd:ref:`proc` and :cmd:ref:`memory` (or :yoscrypt:`memory -nomap`):
|
||||
|
||||
.. figure:: /_images/internals/simplified_rtlil.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:Simplified_RTLIL
|
||||
|
||||
Simplified RTLIL entity-relationship diagram without memories and processes
|
||||
|
@ -140,7 +140,7 @@ We'll do the same as before and format it as a a ``Yosys::Pass``.
|
|||
And if we look at the schematic for this new module we see the following:
|
||||
|
||||
.. figure:: /_images/code_examples/extensions/test1.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
Output of ``yosys -m ./my_cmd.so -p 'test1; show'``
|
||||
|
||||
|
|
|
@ -10,7 +10,7 @@ and generating the data for the next subsystem (see :numref:`Fig. %s
|
|||
<fig:approach_flow>`).
|
||||
|
||||
.. figure:: /_images/internals/approach_flow.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:approach_flow
|
||||
|
||||
General data- and control-flow of a synthesis tool
|
||||
|
|
|
@ -42,7 +42,7 @@ possible it is key that (1) all passes operate on the same data structure
|
|||
design in different stages of the synthesis.
|
||||
|
||||
.. figure:: /_images/internals/overview_flow.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:Overview_flow
|
||||
|
||||
Yosys simplified data flow (ellipses: data structures, rectangles:
|
||||
|
|
|
@ -10,7 +10,7 @@ is then passed to the AST frontend that converts it to RTLIL data, as
|
|||
illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
|
||||
|
||||
.. figure:: /_images/internals/verilog_flow.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:Verilog_flow
|
||||
|
||||
Simplified Verilog to RTLIL data flow
|
||||
|
|
|
@ -661,6 +661,50 @@ The CONFIG parameter carries the following information:
|
|||
|
||||
B is an array of concatenated 1-bit-wide unsigned integers to also be summed up.
|
||||
|
||||
Arbitrary logic functions
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The ``$lut`` cell type implements a single-output LUT (lookup table).
|
||||
It implements an arbitrary logic function with its ``\LUT`` parameter to map
|
||||
input port ``\A`` to values of ``\Y`` output port values.
|
||||
In psuedocode: ``Y = \LUT[A]``.
|
||||
``\A`` has width set by parameter ``\WIDTH`` and ``\Y`` has a width of 1.
|
||||
Every logic function with a single bit output has a unique ``$lut``
|
||||
representation.
|
||||
|
||||
The ``$sop`` cell type implements a sum-of-products expression, also known
|
||||
as disjunctive normal form (DNF). It implements an arbitrary logic function.
|
||||
Its structure mimics a programmable logic array (PLA).
|
||||
Output port ``\Y`` is the sum of products of the bits of the input port ``\A``
|
||||
as defined by parameter ``\TABLE``. ``\A`` is ``\WIDTH`` bits wide.
|
||||
The number of products in the sum is set by parameter ``\DEPTH``, and each
|
||||
product has two bits for each input bit - for the presence of the
|
||||
unnegated and negated version of said input bit in the product.
|
||||
Therefore the ``\TABLE`` parameter holds ``2 * \WIDTH * \DEPTH`` bits.
|
||||
|
||||
For example:
|
||||
|
||||
Let ``\WIDTH`` be 3. We would like to represent ``\Y =~\A[0] + \A[1]~\A[2]``.
|
||||
There are 2 products to be summed, so ``\DEPTH`` shall be 2.
|
||||
|
||||
.. code-block::
|
||||
|
||||
~A[2]-----+
|
||||
A[2]----+|
|
||||
~A[1]---+||
|
||||
A[1]--+|||
|
||||
~A[0]-+||||
|
||||
A[0]+|||||
|
||||
|||||| product formula
|
||||
010000 ~\A[0]
|
||||
001001 \A[1]~\A[2]
|
||||
|
||||
So the value of ``\TABLE`` will become ``010000001001``.
|
||||
|
||||
Any logic function with a single bit output can be represented with
|
||||
``$sop`` but may have variously minimized or ordered summands represented
|
||||
in the ``\TABLE`` values.
|
||||
|
||||
Specify rules
|
||||
~~~~~~~~~~~~~
|
||||
|
||||
|
@ -1192,6 +1236,4 @@ file via ABC using the abc pass.
|
|||
|
||||
.. todo:: Add information about ``$slice`` and ``$concat`` cells.
|
||||
|
||||
.. todo:: Add information about ``$lut`` and ``$sop`` cells.
|
||||
|
||||
.. todo:: Add information about ``$alu``, ``$fa``, and ``$lcu`` cells.
|
||||
|
|
|
@ -24,7 +24,7 @@ create an additional ``RTLIL::Design`` object and call the Verilog frontend with
|
|||
this other object to parse the cell library.
|
||||
|
||||
.. figure:: /_images/internals/overview_rtlil.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
:name: fig:Overview_RTLIL
|
||||
|
||||
Simplified RTLIL Entity-Relationship Diagram
|
||||
|
|
|
@ -34,7 +34,7 @@ Mapping OR3X1
|
|||
:caption: :file:`red_or3x1_map.v`
|
||||
|
||||
.. figure:: /_images/code_examples/techmap/red_or3x1.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/techmap/red_or3x1_test.ys
|
||||
:language: yoscrypt
|
||||
|
@ -61,7 +61,7 @@ Conditional techmap
|
|||
Example:
|
||||
|
||||
.. figure:: /_images/code_examples/techmap/sym_mul.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/techmap/sym_mul_map.v
|
||||
:language: verilog
|
||||
|
@ -100,7 +100,7 @@ Scripting in map modules
|
|||
Example:
|
||||
|
||||
.. figure:: /_images/code_examples/techmap/mymul.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/techmap/mymul_map.v
|
||||
:language: verilog
|
||||
|
@ -130,7 +130,7 @@ Handling constant inputs
|
|||
Example:
|
||||
|
||||
.. figure:: /_images/code_examples/techmap/mulshift.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/techmap/mulshift_map.v
|
||||
:language: verilog
|
||||
|
@ -162,7 +162,7 @@ Handling shorted inputs
|
|||
Example:
|
||||
|
||||
.. figure:: /_images/code_examples/techmap/addshift.*
|
||||
:class: width-helper
|
||||
:class: width-helper invert-helper
|
||||
|
||||
.. literalinclude:: /code_examples/techmap/addshift_map.v
|
||||
:language: verilog
|
||||
|
|
|
@ -10,13 +10,14 @@ import sys
|
|||
logging.basicConfig(level=logging.INFO)
|
||||
|
||||
# expects __file__ = yosys/docs/tests/macro_commands.py
|
||||
TESTS_DIR = Path(__file__).parent
|
||||
TESTS_DIR = Path(__file__).parent.absolute()
|
||||
ROOT_DIR = TESTS_DIR.parent.parent
|
||||
logging.log(logging.INFO, f"Using {ROOT_DIR} as root directory")
|
||||
THIS_FILE = (TESTS_DIR / "macro_commands.py").relative_to(ROOT_DIR)
|
||||
MACRO_SOURCE = TESTS_DIR.parent / "source" / "code_examples" / "macro_commands"
|
||||
assert MACRO_SOURCE.exists(), f"can't find macro_commands in {MACRO_SOURCE}"
|
||||
|
||||
YOSYS = TESTS_DIR.parent.parent / "yosys"
|
||||
YOSYS = ROOT_DIR / "yosys"
|
||||
assert YOSYS.exists(), f"can't find yosys executable in {YOSYS}"
|
||||
|
||||
raise_error = False
|
||||
|
|
|
@ -2156,8 +2156,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
|
|||
int port_offset = 0;
|
||||
if (pr->GetPort()->Bus()) {
|
||||
port_name = pr->GetPort()->Bus()->Name();
|
||||
port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) -
|
||||
min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
|
||||
int msb_index = pr->GetPort()->Bus()->LeftIndex();
|
||||
int lsb_index = pr->GetPort()->Bus()->RightIndex();
|
||||
int index_of_port = pr->GetPort()->Bus()->IndexOf(pr->GetPort());
|
||||
port_offset = index_of_port - min(msb_index, lsb_index);
|
||||
// In cases where the msb order is flipped we need to make sure
|
||||
// that the indicies match LSB = 0 order to match the std::vector
|
||||
// to SigSpec LSB = 0 precondition.
|
||||
if (lsb_index > msb_index) {
|
||||
port_offset = abs(port_offset - (lsb_index - min(msb_index, lsb_index)));
|
||||
}
|
||||
}
|
||||
IdString port_name_id = RTLIL::escape_id(port_name);
|
||||
auto &sigvec = cell_port_conns[port_name_id];
|
||||
|
|
Loading…
Reference in New Issue