diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst index ad7b9613d..08d41702d 100644 --- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst @@ -134,12 +134,12 @@ when the individual bits of of a signal vector are accessed. The key elements in understanding this circuit diagram are of course the boxes with round corners and rows labeled ``: - -:``. Each of this boxes has one signal per row on one side -and a common signal for all rows on the other side. The ``:`` tuples -specify which bits of the signals are broken out and connected. So the top row -of the box connecting the signals ``a`` and ``x`` indicates that the bit 0 (i.e. -the range 0:0) from signal ``a`` is connected to bit 1 (i.e. the range 1:1) of -signal ``x``. +:``. Each of these boxes have one signal per row on one +side and a common signal for all rows on the other side. The ``:`` +tuples specify which bits of the signals are broken out and connected. So the +top row of the box connecting the signals ``a`` and ``x`` indicates that the bit +0 (i.e. the range 0:0) from signal ``a`` is connected to bit 1 (i.e. the range +1:1) of signal ``x``. Lines connecting such boxes together and lines connecting such boxes to cell ports have a slightly different look to emphasise that they are not actual @@ -213,11 +213,11 @@ the ``pdf`` and ``ps`` format are the only formats that support plotting multiple modules in one run. In densely connected circuits it is sometimes hard to keep track of the -individual signal wires. For this cases it can be useful to call :cmd:ref:`show` -with the ``-colors `` argument, which randomly assigns colors to the -nets. The integer (> 0) is used as seed value for the random color assignments. -Sometimes it is necessary it try some values to find an assignment of colors -that looks good. +individual signal wires. For these cases it can be useful to call +:cmd:ref:`show` with the ``-colors `` argument, which randomly assigns +colors to the nets. The integer (> 0) is used as seed value for the random color +assignments. Sometimes it is necessary it try some values to find an assignment +of colors that looks good. The command ``help show`` prints a complete listing of all options supported by the :cmd:ref:`show` command. @@ -531,7 +531,7 @@ Note that the :cmd:ref:`eval` command (as well as the :cmd:ref:`sat` command discussed in the next sections) does only operate on flattened modules. It can not analyze signals that are passed through design hierarchy levels. So the :cmd:ref:`flatten` command must be used on modules that instantiate other -modules before this commands can be applied. +modules before these commands can be applied. Solving combinatorial SAT problems ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/source/using_yosys/more_scripting/selections.rst b/docs/source/using_yosys/more_scripting/selections.rst index eb3f66d6c..6504bc0bb 100644 --- a/docs/source/using_yosys/more_scripting/selections.rst +++ b/docs/source/using_yosys/more_scripting/selections.rst @@ -187,7 +187,7 @@ all cells and signals that are used to generate the signal ``sum``. The ``%ci`` action can be used to select the input cones of all object in the top selection in the stack maintained by the :cmd:ref:`select` command. -As with the ``%x`` action, this commands broadens the selection by one "step". +As with the ``%x`` action, these commands broaden the selection by one "step". But this time the operation only works against the direction of data flow. That means, wires only select cells via output ports and cells only select wires via input ports. @@ -329,7 +329,7 @@ Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts the same syntax for pattern and repetition. The ``%x`` action mentioned previously also accepts this advanced syntax. -This actions for traversing the circuit graph, combined with the actions for +These actions for traversing the circuit graph, combined with the actions for boolean operations such as intersection (``%i``) and difference (``%d``) are powerful tools for extracting the relevant portions of the circuit under investigation. diff --git a/docs/source/yosys_internals/flow/index.rst b/docs/source/yosys_internals/flow/index.rst index e2b5b658c..7733ec855 100644 --- a/docs/source/yosys_internals/flow/index.rst +++ b/docs/source/yosys_internals/flow/index.rst @@ -4,7 +4,7 @@ Internal flow A (usually short) synthesis script controls Yosys. -This scripts contain three types of commands: +These scripts contain three types of commands: - **Frontends**, that read input files (usually Verilog); - **Passes**, that perform transformations on the design in memory; diff --git a/docs/source/yosys_internals/techmap.rst b/docs/source/yosys_internals/techmap.rst index 3bbda4c38..973aca39f 100644 --- a/docs/source/yosys_internals/techmap.rst +++ b/docs/source/yosys_internals/techmap.rst @@ -279,9 +279,9 @@ Notes on using techmap ~~~~~~~~~~~~~~~~~~~~~~ - Don't use positional cell parameters in map modules. -- You can use the ``$__``-prefix for internal cell types to avoid - collisions with the user-namespace. But always use two underscores or the - internal consistency checker will trigger on this cells. +- You can use the ``$__``-prefix for internal cell types to avoid collisions + with the user-namespace. But always use two underscores or the internal + consistency checker will trigger on these cells. - Techmap has two major use cases: - Creating good logic-level representation of arithmetic functions. This