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Do not use log_id as it strips \\, also fix scc for |wire| > 1

This commit is contained in:
Eddie Hung 2019-06-24 22:04:22 -07:00
parent ca0225fcfa
commit babadf5938
1 changed files with 30 additions and 13 deletions
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43
passes/techmap/abc9.cc
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@ -96,11 +96,15 @@ void handle_loops(RTLIL::Design *design)
Wire *w = b.wire; Wire *w = b.wire;
log_assert(!w->port_input); log_assert(!w->port_input);
w->port_input = true; w->port_input = true;
w = module->wire(stringf("%s.abci", log_id(w->name))); w = module->wire(stringf("%s.abci", w->name.c_str()));
if (!w) if (!w) {
w = module->addWire(stringf("%s.abci", log_id(b.wire->name)), GetSize(b.wire)); w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
log_assert(b.offset < GetSize(w)); w->port_output = true;
w->port_output = true; }
else {
log_assert(w->port_input);
log_assert(b.offset < GetSize(w));
}
w->set_bool_attribute("\\abc_scc_break"); w->set_bool_attribute("\\abc_scc_break");
module->swap_names(b.wire, w); module->swap_names(b.wire, w);
c.second = RTLIL::SigBit(w, b.offset); c.second = RTLIL::SigBit(w, b.offset);
@ -118,14 +122,27 @@ void handle_loops(RTLIL::Design *design)
auto &c = *it; auto &c = *it;
SigBit b = cell->getPort(RTLIL::escape_id(jt->second.decode_string())); SigBit b = cell->getPort(RTLIL::escape_id(jt->second.decode_string()));
Wire *w = b.wire; Wire *w = b.wire;
log_assert(!w->port_output); if (w->port_output) {
w->port_output = true; log_assert(w->get_bool_attribute("\\abc_scc_break"));
w->set_bool_attribute("\\abc_scc_break"); w = module->wire(stringf("%s.abci", w->name.c_str()));
w = module->wire(stringf("%s.abci", log_id(w->name))); log_assert(w);
if (!w) log_assert(b.offset < GetSize(w));
w = module->addWire(stringf("%s.abci", log_id(b.wire->name)), GetSize(b.wire)); log_assert(w->port_input);
log_assert(b.offset < GetSize(w)); }
w->port_input = true; else {
log_assert(!w->port_output);
w->port_output = true;
w->set_bool_attribute("\\abc_scc_break");
w = module->wire(stringf("%s.abci", w->name.c_str()));
if (!w) {
w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
w->port_input = true;
}
else {
log_assert(w->port_input);
log_assert(b.offset < GetSize(w));
}
}
c.second = RTLIL::SigBit(w, b.offset); c.second = RTLIL::SigBit(w, b.offset);
} }
} }