mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1277 from YosysHQ/eddie/fix_1262
opt_expr -fine to now trim LSBs of $alu cells too
This commit is contained in:
Eddie Hung
GitHub
commit
ba1a428f55
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@ -641,7 +641,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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if (cell->type.in("$add", "$sub")) {
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if (cell->type.in("$add", "$sub"))
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{
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RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
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RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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@ -665,6 +666,53 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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did_something = true;
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}
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}
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if (cell->type == "$alu")
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{
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RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
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RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
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RTLIL::SigBit sig_ci = assign_map(cell->getPort("\\CI"));
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RTLIL::SigBit sig_bi = assign_map(cell->getPort("\\BI"));
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RTLIL::SigSpec sig_x = cell->getPort("\\X");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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RTLIL::SigSpec sig_co = cell->getPort("\\CO");
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if (sig_ci.wire || sig_bi.wire)
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goto next_cell;
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bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
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// If not a subtraction, yet there is a carry or B is inverted
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// then no optimisation is possible as carry will not be constant
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if (!sub && (sig_ci != State::S0 || sig_bi != State::S0))
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goto next_cell;
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int i;
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for (i = 0; i < GetSize(sig_y); i++) {
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if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) {
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module->connect(sig_x[i], sub ? module->Not(NEW_ID, sig_a[i]).as_bit() : sig_a[i]);
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module->connect(sig_y[i], sig_a[i]);
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module->connect(sig_co[i], sub ? State::S1 : State::S0);
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}
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else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) {
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module->connect(sig_x[i], sig_b[i]);
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module->connect(sig_y[i], sig_b[i]);
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module->connect(sig_co[i], State::S0);
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}
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else
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break;
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}
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if (i > 0) {
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cover("opt.opt_expr.fine.$alu");
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cell->setPort("\\A", sig_a.extract_end(i));
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cell->setPort("\\B", sig_b.extract_end(i));
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cell->setPort("\\X", sig_x.extract_end(i));
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cell->setPort("\\Y", sig_y.extract_end(i));
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cell->setPort("\\CO", sig_co.extract_end(i));
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cell->fixup_parameters();
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did_something = true;
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}
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}
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}
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if (cell->type.in("$reduce_xor", "$reduce_xnor", "$shift", "$shiftx", "$shl", "$shr", "$sshl", "$sshr",
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@ -5,144 +5,219 @@ module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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equiv_opt -assert opt_expr -fine
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design -load postopt
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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equiv_opt -assert opt_expr -fine
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design -load postopt
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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equiv_opt -assert opt_expr -fine
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design -load postopt
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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dump
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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equiv_opt -assert opt_expr -fine
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design -load postopt
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) - j;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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equiv_opt -assert opt_expr -fine
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design -load postopt
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opt_expr -fine
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wreduce
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select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) - j;
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endmodule
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EOT
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alumacc
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opt_expr -fine
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
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assign o = 5'b00010 - i;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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design -save gold
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opt_expr -fine
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wreduce
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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design -stash gate
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##########
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design -import gold -as gold
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design -import gate -as gate
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
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assign o = 5'b00010 - i;
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endmodule
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EOT
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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wreduce
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
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\$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co));
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endmodule
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EOT
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check
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
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\$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co));
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endmodule
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EOT
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check
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
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\$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co));
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endmodule
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EOT
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check
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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