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Using $pos models for $bu0

This commit is contained in:
Clifford Wolf 2014-09-03 21:20:59 +02:00
parent 5733f4a39d
commit b9cb483f3e
3 changed files with 3 additions and 18 deletions
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17
backends/verilog/verilog_backend.cc
View File

@ -538,6 +538,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
HANDLE_UNIOP("$not", "~") HANDLE_UNIOP("$not", "~")
HANDLE_UNIOP("$pos", "+") HANDLE_UNIOP("$pos", "+")
HANDLE_UNIOP("$bu0", "+")
HANDLE_UNIOP("$neg", "-") HANDLE_UNIOP("$neg", "-")
HANDLE_BINOP("$and", "&") HANDLE_BINOP("$and", "&")
@ -651,22 +652,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$bu0")
{
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort("\\Y"));
if (cell->parameters["\\A_SIGNED"].as_bool()) {
f << stringf(" = $signed(");
dump_sigspec(f, cell->getPort("\\A"));
f << stringf(");\n");
} else {
f << stringf(" = { 1'b0, ");
dump_sigspec(f, cell->getPort("\\A"));
f << stringf(" };\n");
}
return true;
}
if (cell->type == "$concat") if (cell->type == "$concat")
{ {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());

2
kernel/calc.cc
View File

@ -575,7 +575,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
{ {
RTLIL::Const arg1_ext = arg1; RTLIL::Const arg1_ext = arg1;
extend(arg1_ext, result_len, signed1); extend_u0(arg1_ext, result_len, signed1);
return arg1_ext; return arg1_ext;
} }

2
kernel/satgen.h
View File

@ -470,7 +470,7 @@ struct SatGen
{ {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0"); extendSignalWidthUnary(undef_a, undef_y, cell);
if (cell->type == "$pos" || cell->type == "$bu0") { if (cell->type == "$pos" || cell->type == "$bu0") {
ez->assume(ez->vec_eq(undef_a, undef_y)); ez->assume(ez->vec_eq(undef_a, undef_y));