riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Supress error for unhandled \init if whole module selected

This commit is contained in:
Eddie Hung 2019-12-11 11:49:13 -08:00
parent 840bb17089
commit b97a9cd3f3
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
passes/techmap/zinit.cc
View File

@ -141,9 +141,10 @@ struct ZinitPass : public Pass {
cell->setPort(ID::Q, initwire); cell->setPort(ID::Q, initwire);
} }
for (auto &it : initbits) if (!design->selected_whole_module(module))
if (donebits.count(it.first) == 0) for (auto &it : initbits)
log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second)); if (donebits.count(it.first) == 0)
log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second));
} }
} }
} ZinitPass; } ZinitPass;