mirror of https://github.com/YosysHQ/yosys.git
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
ad69c668ce
commit
b9545aa0e1
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/ice40_dsp_pm.h
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OBJS += passes/pmgen/ice40_dsp.o
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passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h
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EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h
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.SECONDARY: passes/pmgen/ice40_dsp_pm.h
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passes/pmgen/ice40_dsp_pm.h: passes/pmgen/ice40_dsp.pmg passes/pmgen/pmgen.py
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$(P) cd passes/pmgen && python3 pmgen.py ice40_dsp
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "passes/pmgen/ice40_dsp_pm.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void ice40_dsp_accept(ice40_dsp_pm * /* pm */)
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{
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}
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struct Ice40DspPass : public Pass {
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Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_dsp [options] [selection]\n");
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log("\n");
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log("Map multipliers and iCE40 DSP resources.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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ice40_dsp_pm pm(module);
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pm.run(ice40_dsp_accept);
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}
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}
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} Ice40DspPass;
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PRIVATE_NAMESPACE_END
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@ -1,6 +1,6 @@
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state SigBit clock
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state bool clock_pol, clock_vld
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state SigSpec sigA, sigB, sigY
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state <SigBit> clock
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state <bool> clock_pol clock_vld
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state <SigSpec> sigA sigB sigY
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match mul
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select mul->type.in($mul)
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@ -10,7 +10,8 @@ endmatch
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match ffA
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select ffA->type.in($dff)
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filter port(ffA, \Q) === port(mul, \A)
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select nusers(port(ffA, \Q)) == 2
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filter <SigSpec> port(ffA, \Q) === port(mul, \A)
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optional
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endmatch
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@ -28,11 +29,12 @@ endcode
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match ffB
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select ffB->type.in($dff)
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filter port(ffB, \Q) === port(mul, \B)
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select nusers(port(ffA, \Q)) == 2
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filter <SigSpec> port(ffB, \Q) === port(mul, \B)
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optional
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endmatch
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code sigB clock clok_pol clock_vld
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code sigB clock clock_pol clock_vld
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sigB = port(mul, \B);
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if (ffB != nullptr) {
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@ -51,11 +53,12 @@ endcode
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match ffY
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select ffY->type.in($dff)
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filter port(ffY, \D) === port(mul, \Y)
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select nusers(port(ffY, \D)) == 2
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filter <SigSpec> port(ffY, \D) === port(mul, \Y)
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optional
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endmatch
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code sigY clock clok_pol clock_vld
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code sigY clock clock_pol clock_vld
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sigY = port(mul, \Y);
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if (ffY != nullptr) {
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@ -0,0 +1,262 @@
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#!/usr/bin/env python3
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import re
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import sys
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import pprint
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pp = pprint.PrettyPrinter(indent=4)
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prefix = sys.argv[1]
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state_types = dict()
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blocks = list()
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ids = dict()
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def rewrite_cpp(s):
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t = list()
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i = 0
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while i < len(s):
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if s[i] in ("'", '"') and i + 1 < len(s):
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j = i + 1
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while j + 1 < len(s) and s[j] != s[i]:
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if s[j] == '\\' and j + 1 < len(s):
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j += 1
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j += 1
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t.append(s[i:j+1])
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i = j + 1
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continue
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if s[i] in ('$', '\\') and i + 1 < len(s):
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j = i + 1
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while True:
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if j == len(s):
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j -= 1
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break
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if ord('a') <= ord(s[j]) <= ord('z'):
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j += 1
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continue
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if ord('A') <= ord(s[j]) <= ord('Z'):
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j += 1
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continue
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if ord('0') <= ord(s[j]) <= ord('9'):
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j += 1
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continue
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if s[j] == '_':
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j += 1
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continue
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j -= 1
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break
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n = s[i:j+1]
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i = j + 1
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if n[0] == '$':
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v = "id_d_" + n[1:]
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else:
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v = "id_b_" + n[1:]
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if v not in ids:
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ids[v] = n
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else:
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assert ids[v] == n
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t.append(v)
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continue
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if s[i] == "\t":
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t.append(" ")
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else:
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t.append(s[i])
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i += 1
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return "".join(t)
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with open("%s.pmg" % prefix, "r") as f:
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while True:
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line = f.readline()
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if line == "": break
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line = line.strip()
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cmd = line.split()
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if len(cmd) == 0: continue
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cmd = cmd[0]
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if cmd == "state":
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m = re.match(r"^state\s+<(.*?)>\s+(([A-Za-z_][A-Za-z_0-9]*\s+)*[A-Za-z_][A-Za-z_0-9]*)\s*$", line)
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assert m
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type_str = m.group(1)
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states_str = m.group(2)
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for s in re.split(r"\s+", states_str):
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assert s not in state_types
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state_types[s] = type_str
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continue
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if cmd == "match":
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block = dict()
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block["type"] = "match"
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line = line.split()
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assert len(line) == 2
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assert line[1] not in state_types
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block["cell"] = line[1]
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state_types[line[1]] = "Cell*";
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block["select"] = list()
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block["filter"] = list()
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block["optional"] = False
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while True:
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l = f.readline()
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assert l != ""
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a = l.split()
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if len(a) == 0: continue
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if a[0] == "endmatch": break
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if a[0] == "select":
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b = l.lstrip()[6:]
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block["select"].append(rewrite_cpp(b.strip()))
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continue
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if a[0] == "filter":
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m = re.match(r"^\s*filter\s+<(.*?)>\s+(.*?)\s*===\s*(.*?)\s*$", l)
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assert m
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block["filter"].append((m.group(1), rewrite_cpp(m.group(2)), rewrite_cpp(m.group(3))))
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continue
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if a[0] == "optional":
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block["optional"] = True
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continue
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assert False
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blocks.append(block)
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if cmd == "code":
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block = dict()
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block["type"] = "code"
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block["code"] = list()
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block["states"] = set()
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for s in line.split()[1:]:
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assert s in state_types
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block["states"].add(s)
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while True:
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l = f.readline()
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assert l != ""
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a = l.split()
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if len(a) == 0: continue
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if a[0] == "endcode": break
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block["code"].append(rewrite_cpp(l.rstrip()))
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blocks.append(block)
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# pp.pprint(blocks)
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with open("%s_pm.h" % prefix, "w") as f:
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print("// Generated by pmgen.py from {}.pgm".format(prefix), file=f)
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print("#include \"kernel/yosys.h\"", file=f)
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print("#include \"kernel/sigtools.h\"", file=f)
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print("YOSYS_NAMESPACE_BEGIN", file=f)
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print("struct {}_pm {{".format(prefix), file=f)
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print(" Module *module;", file=f)
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print(" SigMap sigmap;", file=f)
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print(" std::function<void(struct {}_pm*)> on_accept;".format(prefix), file=f)
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print("", file=f)
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for index in range(len(blocks)):
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block = blocks[index]
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if block["type"] == "match":
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index_types = list()
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for filt in block["filter"]:
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index_types.append(filt[0])
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print(" typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f)
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print(" dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
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print(" pool<Cell*> blacklist;", file=f)
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print("", file=f)
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print(" struct state_t {", file=f)
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for s, t in sorted(state_types.items()):
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print(" {} {};".format(t, s), file=f)
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print(" } st;", file=f)
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print("", file=f)
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for v, n in sorted(ids.items()):
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if n[0] == "\\":
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print(" IdString {}{{\"\\{}\"}};".format(v, n), file=f)
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else:
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print(" IdString {}{{\"{}\"}};".format(v, n), file=f)
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print("", file=f)
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print(" {}_pm(Module *module) :".format(prefix), file=f)
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print(" module(module), sigmap(module) {", file=f)
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print(" }", file=f)
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print("", file=f)
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print(" void run(std::function<void(struct {}_pm*)> on_accept_f) {{".format(prefix), file=f)
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print(" on_accept = on_accept_f;", file=f)
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if len(blocks):
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print(" block_0();", file=f)
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print(" }", file=f)
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for index in range(len(blocks)):
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block = blocks[index]
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print("", file=f)
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print(" void block_{}() {{".format(index), file=f)
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const_st = set()
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nonconst_st = set()
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restore_st = set()
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for i in range(index):
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if blocks[i]["type"] == "code":
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for s in blocks[i]["states"]:
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const_st.add(s)
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elif blocks[i]["type"] == "match":
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const_st.add(blocks[i]["cell"])
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else:
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assert False
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if block["type"] == "code":
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for s in block["states"]:
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if s in const_st:
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const_st.remove(s)
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restore_st.add(s)
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nonconst_st.add(s)
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elif block["type"] == "match":
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s = block["cell"]
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assert s not in const_st
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nonconst_st.add(s)
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else:
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assert False
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for s in sorted(const_st):
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t = state_types[s]
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if t.endswith("*"):
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print(" {} const &{} YS_ATTRIBUTE(unused) = st.{};".format(t, s, s), file=f)
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else:
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print(" const {} &{} YS_ATTRIBUTE(unused) = st.{};".format(t, s, s), file=f)
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for s in sorted(nonconst_st):
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t = state_types[s]
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print(" {} &{} YS_ATTRIBUTE(unused) = st.{};".format(t, s, s), file=f)
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if len(restore_st):
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print("", file=f)
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for s in sorted(restore_st):
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t = state_types[s]
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print(" {} backup_{} = st.{};".format(t, s, s), file=f)
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if len(restore_st):
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print("", file=f)
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for s in sorted(restore_st):
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t = state_types[s]
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print(" st.{} = backup_{};".format(s, s), file=f)
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print(" }", file=f)
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print("};\nYOSYS_NAMESPACE_END", file=f)
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