From 19271bd996a79cb4be1db658fcf18227ee0a1dff Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 14:42:25 -0700 Subject: [PATCH 01/14] abc -dff now implies "-D 0" otherwise retiming doesn't happen --- passes/techmap/abc.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 21b70f492..c828ad8ed 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1674,6 +1674,8 @@ struct AbcPass : public Pass { } if (arg == "-dff") { dff_mode = true; + if (delay_target.empty()) + delay_target = "-D 0"; continue; } if (arg == "-clk" && argidx+1 < args.size()) { From ff0912c75e2b15c02c9512466179e4b2a15eb3d1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 14:43:06 -0700 Subject: [PATCH 02/14] synth_xilinx to techmap FFs after abc call, otherwise -retime fails --- techlibs/xilinx/synth_xilinx.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 805ae8e6e..99c2be420 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -256,9 +256,9 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -full"); if (vpr) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); } else { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } Pass::call(design, "hierarchy -check"); @@ -269,7 +269,7 @@ struct SynthXilinxPass : public Pass { Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); - Pass::call(design, "techmap -map +/xilinx/lut_map.v"); + Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); } if (check_label(active, run_from, run_to, "map_cells")) From 8b6085254a962da46d46724f2333abd076d32928 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 15:15:13 -0700 Subject: [PATCH 03/14] Resolve @daveshah1 comment, update synth_xilinx help --- techlibs/xilinx/ff_map.v | 8 ++++---- techlibs/xilinx/synth_xilinx.cc | 8 +++++--- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index 13beaa6ae..c323206e8 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -28,14 +28,14 @@ module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPL module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule -module \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule +module \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PN0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule `endif diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 99c2be420..abc164533 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -110,13 +110,14 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); + log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); - log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n"); - log(" abc -lut 5 [-dff] (with '-vpr' only!)\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); + log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); @@ -260,6 +261,7 @@ struct SynthXilinxPass : public Pass } else { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); From 3c253818cab2013dc4db55732d3e21cfa0dc3f19 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 15:30:19 -0700 Subject: [PATCH 04/14] "&nf -D 0" fails => use "-D 1" instead --- passes/techmap/abc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index c828ad8ed..4876f3009 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1675,7 +1675,7 @@ struct AbcPass : public Pass { if (arg == "-dff") { dff_mode = true; if (delay_target.empty()) - delay_target = "-D 0"; + delay_target = "-D 1"; continue; } if (arg == "-clk" && argidx+1 < args.size()) { From 23a6533e98df384afdeb38891404da17533c836b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 15:31:54 -0700 Subject: [PATCH 05/14] Retry --- techlibs/xilinx/ff_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index c323206e8..3d5f78770 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -30,7 +30,7 @@ module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPL module \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PN0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule module \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule From 97587015748eb9f7e0d55a1121f604b8b462b45a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 15:39:05 -0700 Subject: [PATCH 06/14] Move techamp t:$_DFF_?N? to before abc call --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index abc164533..397c83ac6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -111,10 +111,10 @@ struct SynthXilinxPass : public Pass log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); - log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); + log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); @@ -261,7 +261,6 @@ struct SynthXilinxPass : public Pass } else { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); @@ -269,6 +268,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); From d55902300772d90aee09555d412079e17fd4bde7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 16:28:14 -0700 Subject: [PATCH 07/14] Fix S0 -> S1 --- passes/techmap/abc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 4876f3009..e2a152348 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1728,7 +1728,7 @@ struct AbcPass : public Pass { signal_init[initsig[i]] = State::S0; break; case State::S1: - signal_init[initsig[i]] = State::S0; + signal_init[initsig[i]] = State::S1; break; default: break; From ad602438b8313c3dd243c5fabf6f20036487d1ba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 16:28:46 -0700 Subject: [PATCH 08/14] Add retime test --- tests/simple/retime.v | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 tests/simple/retime.v diff --git a/tests/simple/retime.v b/tests/simple/retime.v new file mode 100644 index 000000000..30b6087dc --- /dev/null +++ b/tests/simple/retime.v @@ -0,0 +1,6 @@ +module retime_test(input clk, input [7:0] a, output z); + reg [7:0] ff = 8'hF5; + always @(posedge clk) + ff <= {ff[6:0], ^a}; + assign z = ff[7]; +endmodule From 78d35a86c0e94f1c5e1606f9953d1f340132f02e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 08:31:35 -0700 Subject: [PATCH 09/14] Revert ""&nf -D 0" fails => use "-D 1" instead" This reverts commit 3c253818cab2013dc4db55732d3e21cfa0dc3f19. --- passes/techmap/abc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index e2a152348..f94fc7589 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1675,7 +1675,7 @@ struct AbcPass : public Pass { if (arg == "-dff") { dff_mode = true; if (delay_target.empty()) - delay_target = "-D 1"; + delay_target = "-D 0"; continue; } if (arg == "-clk" && argidx+1 < args.size()) { From 5f4024ffd2a59e3c0c7edce4057c47d3a005e18f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 08:31:40 -0700 Subject: [PATCH 10/14] Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen" This reverts commit 19271bd996a79cb4be1db658fcf18227ee0a1dff. --- passes/techmap/abc.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index f94fc7589..3adbe0a04 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1674,8 +1674,6 @@ struct AbcPass : public Pass { } if (arg == "-dff") { dff_mode = true; - if (delay_target.empty()) - delay_target = "-D 0"; continue; } if (arg == "-clk" && argidx+1 < args.size()) { From 9a6da9a79a22e984ee3eec02caa230b66f10e11a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 08:32:53 -0700 Subject: [PATCH 11/14] synth_* with -retime option now calls abc with -D 1 as well --- techlibs/achronix/synth_achronix.cc | 4 ++-- techlibs/anlogic/synth_anlogic.cc | 2 +- techlibs/coolrunner2/synth_coolrunner2.cc | 2 +- techlibs/easic/synth_easic.cc | 2 +- techlibs/ecp5/synth_ecp5.cc | 2 +- techlibs/gowin/synth_gowin.cc | 2 +- techlibs/greenpak4/synth_greenpak4.cc | 2 +- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/intel/synth_intel.cc | 6 +++--- techlibs/sf2/synth_sf2.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 11 files changed, 15 insertions(+), 15 deletions(-) diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc index 626860d9c..3dbf20911 100755 --- a/techlibs/achronix/synth_achronix.cc +++ b/techlibs/achronix/synth_achronix.cc @@ -152,12 +152,12 @@ struct SynthAchronixPass : public ScriptPass { run("clean -purge"); run("setundef -undriven -zero"); if (retime || help_mode) - run("abc -markgroups -dff", "(only if -retime)"); + run("abc -markgroups -dff -D 1", "(only if -retime)"); } if (check_label("map_luts")) { - run("abc -lut 4" + string(retime ? " -dff" : "")); + run("abc -lut 4" + string(retime ? " -dff -D 1" : "")); run("clean"); } diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 620bf3965..258e3d722 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -164,7 +164,7 @@ struct SynthAnlogicPass : public ScriptPass run("opt -undriven -fine"); run("techmap -map +/techmap.v -map +/anlogic/arith_map.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index 21bbcaef4..fa4fe0f5b 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -161,7 +161,7 @@ struct SynthCoolrunner2Pass : public ScriptPass if (check_label("map_pla")) { - run("abc -sop -I 40 -P 56"); + run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : "")); run("clean"); } diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc index dd9e3dab7..7bacc7890 100644 --- a/techlibs/easic/synth_easic.cc +++ b/techlibs/easic/synth_easic.cc @@ -158,7 +158,7 @@ struct SynthEasicPass : public ScriptPass run("techmap"); run("opt -fast"); if (retime || help_mode) { - run("abc -dff", " (only if -retime)"); + run("abc -dff -D 1", " (only if -retime)"); run("opt_clean", "(only if -retime)"); } } diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 4b889d672..45f101451 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -242,7 +242,7 @@ struct SynthEcp5Pass : public ScriptPass else run("techmap -map +/techmap.v -map +/ecp5/arith_map.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 9a3fcdbb6..0ebd77d63 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -163,7 +163,7 @@ struct SynthGowinPass : public ScriptPass run("splitnets -ports"); run("setundef -undriven -zero"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_luts")) diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index eeb001b46..3222be2e3 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -165,7 +165,7 @@ struct SynthGreenPAK4Pass : public ScriptPass run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib"); run("opt -fast"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_luts")) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 8899bfcc4..d114b6269 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -274,7 +274,7 @@ struct SynthIce40Pass : public ScriptPass else run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); run("ice40_opt"); } diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 0f1d7a7b5..290282bd9 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -210,15 +210,15 @@ struct SynthIntelPass : public ScriptPass { run("clean -purge"); run("setundef -undriven -zero"); if (retime || help_mode) - run("abc -markgroups -dff", "(only if -retime)"); + run("abc -markgroups -dff -D 1", "(only if -retime)"); } if (check_label("map_luts")) { if(family_opt=="a10gx" || family_opt=="cyclonev") - run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); + run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : "")); else - run("abc -lut 4" + string(retime ? " -dff" : "")); + run("abc -lut 4" + string(retime ? " -dff -D 1" : "")); run("clean"); } diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc index 0924df7a6..3c5a58b4c 100644 --- a/techlibs/sf2/synth_sf2.cc +++ b/techlibs/sf2/synth_sf2.cc @@ -181,7 +181,7 @@ struct SynthSf2Pass : public ScriptPass run("opt -undriven -fine"); run("techmap -map +/techmap.v -map +/sf2/arith_map.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 397c83ac6..a462b9052 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -115,7 +115,7 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_luts:\n"); log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); - log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff -D 1]\n"); log(" clean\n"); log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); log("\n"); @@ -269,7 +269,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); - Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); } From 6008bb7002f874e5c748eaa2050e7b6c17b32745 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Apr 2019 07:59:16 -0700 Subject: [PATCH 12/14] Revert "synth_* with -retime option now calls abc with -D 1 as well" This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a. --- techlibs/achronix/synth_achronix.cc | 4 ++-- techlibs/anlogic/synth_anlogic.cc | 2 +- techlibs/coolrunner2/synth_coolrunner2.cc | 2 +- techlibs/easic/synth_easic.cc | 2 +- techlibs/ecp5/synth_ecp5.cc | 2 +- techlibs/gowin/synth_gowin.cc | 2 +- techlibs/greenpak4/synth_greenpak4.cc | 2 +- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/intel/synth_intel.cc | 6 +++--- techlibs/sf2/synth_sf2.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 11 files changed, 15 insertions(+), 15 deletions(-) diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc index 3dbf20911..626860d9c 100755 --- a/techlibs/achronix/synth_achronix.cc +++ b/techlibs/achronix/synth_achronix.cc @@ -152,12 +152,12 @@ struct SynthAchronixPass : public ScriptPass { run("clean -purge"); run("setundef -undriven -zero"); if (retime || help_mode) - run("abc -markgroups -dff -D 1", "(only if -retime)"); + run("abc -markgroups -dff", "(only if -retime)"); } if (check_label("map_luts")) { - run("abc -lut 4" + string(retime ? " -dff -D 1" : "")); + run("abc -lut 4" + string(retime ? " -dff" : "")); run("clean"); } diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 258e3d722..620bf3965 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -164,7 +164,7 @@ struct SynthAnlogicPass : public ScriptPass run("opt -undriven -fine"); run("techmap -map +/techmap.v -map +/anlogic/arith_map.v"); if (retime || help_mode) - run("abc -dff -D 1", "(only if -retime)"); + run("abc -dff", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index fa4fe0f5b..21bbcaef4 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -161,7 +161,7 @@ struct SynthCoolrunner2Pass : public ScriptPass if (check_label("map_pla")) { - run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : "")); + run("abc -sop -I 40 -P 56"); run("clean"); } diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc index 7bacc7890..dd9e3dab7 100644 --- a/techlibs/easic/synth_easic.cc +++ b/techlibs/easic/synth_easic.cc @@ -158,7 +158,7 @@ struct SynthEasicPass : public ScriptPass run("techmap"); run("opt -fast"); if (retime || help_mode) { - run("abc -dff -D 1", " (only if -retime)"); + run("abc -dff", " (only if -retime)"); run("opt_clean", "(only if -retime)"); } } diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 45f101451..4b889d672 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -242,7 +242,7 @@ struct SynthEcp5Pass : public ScriptPass else run("techmap -map +/techmap.v -map +/ecp5/arith_map.v"); if (retime || help_mode) - run("abc -dff -D 1", "(only if -retime)"); + run("abc -dff", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 0ebd77d63..9a3fcdbb6 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -163,7 +163,7 @@ struct SynthGowinPass : public ScriptPass run("splitnets -ports"); run("setundef -undriven -zero"); if (retime || help_mode) - run("abc -dff -D 1", "(only if -retime)"); + run("abc -dff", "(only if -retime)"); } if (check_label("map_luts")) diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 3222be2e3..eeb001b46 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -165,7 +165,7 @@ struct SynthGreenPAK4Pass : public ScriptPass run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib"); run("opt -fast"); if (retime || help_mode) - run("abc -dff -D 1", "(only if -retime)"); + run("abc -dff", "(only if -retime)"); } if (check_label("map_luts")) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index d114b6269..8899bfcc4 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -274,7 +274,7 @@ struct SynthIce40Pass : public ScriptPass else run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); if (retime || help_mode) - run("abc -dff -D 1", "(only if -retime)"); + run("abc -dff", "(only if -retime)"); run("ice40_opt"); } diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 290282bd9..0f1d7a7b5 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -210,15 +210,15 @@ struct SynthIntelPass : public ScriptPass { run("clean -purge"); run("setundef -undriven -zero"); if (retime || help_mode) - run("abc -markgroups -dff -D 1", "(only if -retime)"); + run("abc -markgroups -dff", "(only if -retime)"); } if (check_label("map_luts")) { if(family_opt=="a10gx" || family_opt=="cyclonev") - run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : "")); + run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else - run("abc -lut 4" + string(retime ? " -dff -D 1" : "")); + run("abc -lut 4" + string(retime ? " -dff" : "")); run("clean"); } diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc index 3c5a58b4c..0924df7a6 100644 --- a/techlibs/sf2/synth_sf2.cc +++ b/techlibs/sf2/synth_sf2.cc @@ -181,7 +181,7 @@ struct SynthSf2Pass : public ScriptPass run("opt -undriven -fine"); run("techmap -map +/techmap.v -map +/sf2/arith_map.v"); if (retime || help_mode) - run("abc -dff -D 1", "(only if -retime)"); + run("abc -dff", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a462b9052..397c83ac6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -115,7 +115,7 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_luts:\n"); log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); - log(" abc -luts 2:2,3,6:5,10,20 [-dff -D 1]\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); log("\n"); @@ -269,7 +269,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); - Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : "")); + Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); } From 9aa94370a54c016421740d2ce32ef0aa338d0dbd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Apr 2019 08:46:41 -0700 Subject: [PATCH 13/14] ABC to call retime all the time --- passes/techmap/abc.cc | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 3adbe0a04..aaf580eff 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -29,17 +29,17 @@ // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting -#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" -#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" -#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" -#define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" +#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put" +#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" +#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; if; mfs2" +#define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; cover {I} {P}" +#define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put" -#define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}" -#define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p" -#define ABC_FAST_COMMAND_LUT "strash; dretime; if" -#define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}" -#define ABC_FAST_COMMAND_DFL "strash; dretime; map" +#define ABC_FAST_COMMAND_LIB "strash; dretime; retime {D}; map {D}" +#define ABC_FAST_COMMAND_CTR "strash; dretime; retime {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p" +#define ABC_FAST_COMMAND_LUT "strash; dretime; retime {D}; if" +#define ABC_FAST_COMMAND_SOP "strash; dretime; retime {D}; cover -I {I} -P {P}" +#define ABC_FAST_COMMAND_DFL "strash; dretime; retime {D}; map" #include "kernel/register.h" #include "kernel/sigtools.h" @@ -731,10 +731,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin else abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL; - if (script_file.empty() && !delay_target.empty()) - for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1)) - abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8); - for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos)) abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3); From 070a2d2fd6b2d79a71be1ab5b8fe40e40e690433 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Apr 2019 09:55:03 -0700 Subject: [PATCH 14/14] Fix abc's remap_name to not ignore [^0-9] when extracting sid --- passes/techmap/abc.cc | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index aaf580eff..547115459 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -331,19 +331,23 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp { std::string abc_sname = abc_name.substr(1); if (abc_sname.substr(0, 5) == "ys__n") { - int sid = std::stoi(abc_sname.substr(5)); bool inv = abc_sname.back() == 'v'; - for (auto sig : signal_list) { - if (sig.id == sid && sig.bit.wire != nullptr) { - std::stringstream sstr; - sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1); - if (sig.bit.wire->width != 1) - sstr << "[" << sig.bit.offset << "]"; - if (inv) - sstr << "_inv"; - if (orig_wire != nullptr) - *orig_wire = sig.bit.wire; - return sstr.str(); + if (inv) abc_sname.pop_back(); + abc_sname.erase(0, 5); + if (abc_sname.find_last_not_of("012345689") == std::string::npos) { + int sid = std::stoi(abc_sname); + for (auto sig : signal_list) { + if (sig.id == sid && sig.bit.wire != nullptr) { + std::stringstream sstr; + sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1); + if (sig.bit.wire->width != 1) + sstr << "[" << sig.bit.offset << "]"; + if (inv) + sstr << "_inv"; + if (orig_wire != nullptr) + *orig_wire = sig.bit.wire; + return sstr.str(); + } } } }