From b824a56cde5aa692da2dc6b6a0d161a98daac6ef Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 13:58:10 -0700 Subject: [PATCH] Comment to explain separating CREG packing --- passes/pmgen/xilinx_dsp.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 86472feb5..a145ab184 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -606,6 +606,14 @@ struct XilinxDspPass : public Pass { xilinx_dsp_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_pack(xilinx_dsp_pack); } + // Separating out CREG packing is necessary since there + // is no guarantee that the cell ordering corresponds + // to the "expected" case (i.e. the order in which + // they appear in the source) thus the possiblity + // existed that a register got packed as CREG into a + // downstream DSP that should have otherwise been a + // PREG of an upstream DSP that had not been pattern + // matched yet { xilinx_dsp_CREG_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_packC(xilinx_dsp_packC);