mirror of https://github.com/YosysHQ/yosys.git
write_xaiger to flatten 1'bx/1'bz to 1'b0 again
This commit is contained in:
parent
242b72d4e1
commit
b810bf26ab
|
@ -104,8 +104,10 @@ struct XAigerWriter
|
||||||
aig_map[bit] = bit2aig(alias_map.at(bit));
|
aig_map[bit] = bit2aig(alias_map.at(bit));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (bit == State::Sx || bit == State::Sz)
|
if (bit == State::Sx || bit == State::Sz) {
|
||||||
log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
|
log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit));
|
||||||
|
aig_map[bit] = 0;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
log_assert(aig_map.at(bit) >= 0);
|
log_assert(aig_map.at(bit) >= 0);
|
||||||
|
|
Loading…
Reference in New Issue