mirror of https://github.com/YosysHQ/yosys.git
keep $mux and $_MUX_ optimizations separate in opt_const
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@ -113,7 +113,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
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if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1));
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if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1));
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}
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}
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if (cell->type == "$_MUX_" ||(cell->type == "$mux" && cell->parameters["\\WIDTH"].as_int() == 1)) {
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if (cell->type == "$_MUX_") {
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RTLIL::SigSpec input;
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RTLIL::SigSpec input;
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input.append(cell->connections["\\S"]);
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input.append(cell->connections["\\S"]);
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input.append(cell->connections["\\B"]);
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input.append(cell->connections["\\B"]);
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@ -128,8 +128,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
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// TODO: "10 " -> replace with "!S" gate
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// TODO: "10 " -> replace with "!S" gate
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// TODO: "0 " -> replace with "B AND S" gate
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// TODO: "0 " -> replace with "B AND S" gate
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// TODO: " 1 " -> replace with "A OR S" gate
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// TODO: " 1 " -> replace with "A OR S" gate
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// TODO: "1 " -> replace with "B OR !S" gate
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// TODO: "1 " -> replace with "B OR !S" gate (?)
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// TODO: " 0 " -> replace with "A AND !S" gate
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// TODO: " 0 " -> replace with "A AND !S" gate (?)
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if (input.match(" *")) ACTION_DO_Y(x);
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if (input.match(" *")) ACTION_DO_Y(x);
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#endif
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#endif
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}
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}
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