mirror of https://github.com/YosysHQ/yosys.git
equiv: Suggest running async2sync or clk2fflogic where appropriate.
See #2713.
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@ -55,6 +55,9 @@ struct EquivInductWorker
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for (auto cell : cells) {
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if (!satgen.importCell(cell, step) && !cell_warn_cache.count(cell)) {
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if (RTLIL::builtin_ff_cell_types().count(cell->type))
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log_warning("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type));
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else
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log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
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cell_warn_cache.insert(cell);
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}
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@ -184,8 +184,12 @@ struct EquivSimpleWorker
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for (auto cell : problem_cells) {
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auto key = pair<Cell*, int>(cell, step+1);
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if (!imported_cells_cache.count(key) && !satgen.importCell(cell, step+1))
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if (!imported_cells_cache.count(key) && !satgen.importCell(cell, step+1)) {
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if (RTLIL::builtin_ff_cell_types().count(cell->type))
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log_cmd_error("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type));
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else
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log_cmd_error("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
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}
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imported_cells_cache.insert(key);
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}
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