riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add "WE" to dist RAM's abc_scc_break

This commit is contained in:
Eddie Hung 2019-06-26 19:58:09 -07:00
parent 26efd6f0a9
commit b7bef15b16
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
techlibs/xilinx/cells_sim.v
View File

@ -281,7 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule endmodule
(* abc_box_id = 4, abc_scc_break="D" *) (* abc_box_id = 4, abc_scc_break="D,WE" *)
module RAM32X1D ( module RAM32X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,
@ -299,7 +299,7 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D; always @(posedge clk) if (WE) mem[a] <= D;
endmodule endmodule
(* abc_box_id = 5, abc_scc_break="D" *) (* abc_box_id = 5, abc_scc_break="D,WE" *)
module RAM64X1D ( module RAM64X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,
@ -317,7 +317,7 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D; always @(posedge clk) if (WE) mem[a] <= D;
endmodule endmodule
(* abc_box_id = 6, abc_scc_break="D" *) (* abc_box_id = 6, abc_scc_break="D,WE" *)
module RAM128X1D ( module RAM128X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,