mirror of https://github.com/YosysHQ/yosys.git
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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module bar(clk, rst, inp, out);
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input wire clk;
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input wire rst;
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input wire inp;
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output reg out;
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always @(posedge clk)
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if (rst) out <= 1'd0;
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else out <= ~inp;
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endmodule
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module foo(clk, rst, inp, out);
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input wire clk;
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input wire rst;
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input wire inp;
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output wire out;
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bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
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endmodule
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# Read and parse Verilog file
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read_verilog attrib05_port_conn.v
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function [7:0] do_add;
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input [7:0] inp_a;
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input [7:0] inp_b;
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do_add = inp_a + inp_b;
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endfunction
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module foo(clk, rst, inp_a, inp_b, out);
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input wire clk;
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input wire rst;
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input wire [7:0] inp_a;
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input wire [7:0] inp_b;
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output wire [7:0] out;
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always @(posedge clk)
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if (rst) out <= 0;
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else out <= do_add (* combinational_adder *) (inp_a, inp_b);
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endmodule
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# Read and parse Verilog file
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read_verilog attrib07_func_call.v
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