mirror of https://github.com/YosysHQ/yosys.git
fixed memory next issue, when same memory is written in different case statement
fixed reduce_xnor, logic_not bug translation bug
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2446b6fbef
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b783dbe148
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@ -75,6 +75,7 @@ struct BtorDumper
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std::string str;//temp string for writing file
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std::map<RTLIL::IdString, bool> basic_wires;//input wires and registers
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RTLIL::IdString curr_cell; //current cell being dumped
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std::set<int> mem_next; //if memory (line_number) already has next
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std::map<std::string, std::string> cell_type_translation, s_cell_type_translation; //RTLIL to BTOR translation
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BtorDumper(FILE *f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
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f(f), module(module), design(design), config(config), ct(design), sigmap(module)
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@ -414,7 +415,7 @@ struct BtorDumper
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line_ref[cell->name]=cell_line;
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}
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//unary cells
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if(cell->type == "$not" || cell->type == "$neg" || cell->type == "$pos" || cell->type == "$reduce_and" ||
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else if(cell->type == "$not" || cell->type == "$neg" || cell->type == "$pos" || cell->type == "$reduce_and" ||
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cell->type == "$reduce_or" || cell->type == "$reduce_xor" || cell->type == "$reduce_bool")
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{
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log("writing unary cell - %s\n", cstr(cell->type));
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@ -451,15 +452,17 @@ struct BtorDumper
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++line_num;
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str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_or").c_str(), output_width, l);
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fprintf(f, "%s\n", str.c_str());
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l = line_num;
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}
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else if(cell->type == "$reduce_xnor")
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{
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++line_num;
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str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_xor").c_str(), output_width, l);
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fprintf(f, "%s\n", str.c_str());
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l = line_num;
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}
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++line_num;
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str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$not").c_str(), output_width, line_num-1);
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str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$not").c_str(), output_width, l);
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fprintf(f, "%s\n", str.c_str());
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line_ref[cell->name]=line_num;
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}
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@ -661,13 +664,13 @@ struct BtorDumper
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}
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++line_num;
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str = stringf ("%d cond 1 %d %d %d", line_num, c[select_width-1], c[select_width-1]+1, default_case);
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str = stringf ("%d cond %d %d %d %d", line_num, output_width, c[select_width-1], c[select_width-1]+1, default_case);
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fprintf(f, "%s\n", str.c_str());
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for (int i=select_width-2; i>=0; --i)
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{
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++line_num;
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str = stringf ("%d cond 1 %d %d %d", line_num, c[i], c[i]+1, line_num-1);
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str = stringf ("%d cond %d %d %d %d", line_num, output_width, c[i], c[i]+1, line_num-1);
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fprintf(f, "%s\n", str.c_str());
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}
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@ -767,6 +770,21 @@ struct BtorDumper
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int data = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\DATA")), data_width);
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str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
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int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
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//check if the memory has already next
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auto it = mem_next.find(mem);
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if(it != std::end(mem_next))
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{
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++line_num;
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str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
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RTLIL::Memory *memory = module->memories.at(RTLIL::IdString(str.c_str()));
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int address_bits = ceil(log(memory->size)/log(2));
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str = stringf("%d array %d %d", line_num, memory->width, address_bits);
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fprintf(f, "%s\n", str.c_str());
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++line_num;
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str = stringf("%d eq 1 %d %d", line_num, mem, line_num - 1);
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fprintf(f, "%s\n", str.c_str());
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mem = line_num - 1;
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}
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++line_num;
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if(polarity)
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str = stringf("%d one 1", line_num);
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@ -788,6 +806,7 @@ struct BtorDumper
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++line_num;
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str = stringf("%d anext %d %d %d %d", line_num, data_width, address_width, mem, line_num-1);
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fprintf(f, "%s\n", str.c_str());
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mem_next.insert(mem);
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line_ref[cell->name]=line_num;
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}
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else if(cell->type == "$slice")
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