mirror of https://github.com/YosysHQ/yosys.git
Revert "Revert "Move ff_map back after ABC for shregmap""
This reverts commit e473e74565
.
This commit is contained in:
parent
a1d4ae78a0
commit
b77c5da769
|
@ -291,9 +291,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
if (check_label("map_cells")) {
|
||||
if (!nomux || help_mode)
|
||||
run("muxcover -mux8 -mux16", "(skip if '-nomux')");
|
||||
run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
|
||||
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
|
||||
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
|
||||
run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
|
@ -309,8 +307,10 @@ struct SynthXilinxPass : public ScriptPass
|
|||
// This shregmap call infers fixed length shift registers after abc
|
||||
// has performed any necessary retiming
|
||||
if (!nosrl || help_mode)
|
||||
run("shregmap -tech xilinx_static -minlen 3", "(skip if '-nosrl')");
|
||||
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
|
||||
run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
|
||||
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
|
||||
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
|
||||
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue