Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf

efinix: Nuke efinix_gbuf in favor of clkbufmap.

techlibs/efinix/Makefile.inc

@@ -1,10 +1,10 @@
 
 OBJS += techlibs/efinix/synth_efinix.o
-OBJS += techlibs/efinix/efinix_gbuf.o
 OBJS += techlibs/efinix/efinix_fixcarry.o
 
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/gbuf_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt))

techlibs/efinix/cells_sim.v

@@ -36,6 +36,7 @@ module EFX_FF(
    output reg Q,
    input D,
    input CE,
+   (* clkbuf_sink *)
    input CLK,
    input SR
 );
@@ -100,6 +101,7 @@ endmodule
 module EFX_GBUFCE(
    input CE,
    input I,
+   (* clkbuf_driver *)
    output O
 );
    parameter CE_POLARITY = 1'b1;
@@ -115,11 +117,13 @@ module EFX_RAM_5K(
    input [WRITE_WIDTH-1:0] WDATA,
    input [WRITE_ADDR_WIDTH-1:0] WADDR,
    input WE, 
+   (* clkbuf_sink *)
    input WCLK,
    input WCLKE, 
    output [READ_WIDTH-1:0] RDATA, 
    input [READ_ADDR_WIDTH-1:0] RADDR,
    input RE, 
+   (* clkbuf_sink *)
    input RCLK
 );
    parameter READ_WIDTH = 20;
@@ -172,4 +176,4 @@ module EFX_RAM_5K(
 			    (WRITE_WIDTH == 10) ? 9 :  // 512x10
 			    (WRITE_WIDTH == 5)  ? 10 : -1; // 1024x5
    
-endmodule
+endmodule

techlibs/efinix/efinix_gbuf.cc

@@ -1,119 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2019  Miodrag Milanovic <miodrag@symbioticeda.com>
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-static void handle_gbufs(Module *module)
-{
-	SigMap sigmap(module);
-
-	pool<SigBit> clk_bits;
-	dict<SigBit, SigBit> rewrite_bits;
-	vector<pair<Cell*, SigBit>> pad_bits;
-
-	for (auto cell : module->cells())
-	{
-		if (cell->type == ID(EFX_FF)) {
-			for (auto bit : sigmap(cell->getPort(ID::CLK)))
-				clk_bits.insert(bit);
-		}
-		if (cell->type == ID(EFX_RAM_5K)) {
-			for (auto bit : sigmap(cell->getPort(ID(RCLK))))
-				clk_bits.insert(bit);
-			for (auto bit : sigmap(cell->getPort(ID(WCLK))))
-				clk_bits.insert(bit);
-		}
-	}
-
-	for (auto wire : vector<Wire*>(module->wires()))
-	{
-		if (!wire->port_input)
-			continue;
-
-		for (int index = 0; index < GetSize(wire); index++)
-		{
-			SigBit bit(wire, index);
-			SigBit canonical_bit = sigmap(bit);
-
-			if (!clk_bits.count(canonical_bit))
-				continue;
-
-			Cell *c = module->addCell(NEW_ID, ID(EFX_GBUFCE));
-			SigBit new_bit = module->addWire(NEW_ID);
-			c->setParam(ID(CE_POLARITY), State::S1);
-			c->setPort(ID::O, new_bit);
-			c->setPort(ID(CE), State::S1);
-			pad_bits.push_back(make_pair(c, bit));
-			rewrite_bits[canonical_bit] = new_bit;
-
-			log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
-		}
-	}
-
-	auto rewrite_function = [&](SigSpec &s) {
-		for (auto &bit : s) {
-			SigBit canonical_bit = sigmap(bit);
-			if (rewrite_bits.count(canonical_bit))
-				bit = rewrite_bits.at(canonical_bit);
-		}
-	};
-
-	module->rewrite_sigspecs(rewrite_function);
-
-	for (auto &it : pad_bits)
-		it.first->setPort(ID::I, it.second);
-}
-
-struct EfinixGbufPass : public Pass {
-	EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { }
-	void help() override
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("    efinix_gbuf [options] [selection]\n");
-		log("\n");
-		log("Add Efinix global clock buffers to top module as needed.\n");
-		log("\n");
-	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-	{
-		log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n");
-		
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			break;
-		}
-		extra_args(args, argidx, design);
-
-		Module *module = design->top_module();
-
-		if (module == nullptr)
-			log_cmd_error("No top module found.\n");
-
-		handle_gbufs(module);		
-	}
-} EfinixGbufPass;
-
-PRIVATE_NAMESPACE_END

techlibs/efinix/gbuf_map.v

@@ -0,0 +1,3 @@
+module \$__EFX_GBUF (input I, output O);
+  EFX_GBUFCE #(.CE_POLARITY(1'b1)) _TECHMAP_REPLACE_ (.I(I), .O(O), .CE(1'b1));
+endmodule

techlibs/efinix/synth_efinix.cc

@@ -202,7 +202,8 @@ struct SynthEfinixPass : public ScriptPass
 
 		if (check_label("map_gbuf"))
 		{
-			run("efinix_gbuf");
+			run("clkbufmap -buf $__EFX_GBUF O:I");
+			run("techmap -map +/efinix/gbuf_map.v");
 			run("efinix_fixcarry");
 			run("clean");
 		}