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Added "test_cell -muxdiv"

This commit is contained in:
Clifford Wolf 2014-12-25 19:22:39 +01:00
parent 68233baa1f
commit b748622a7f
1 changed files with 18 additions and 2 deletions
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20
passes/tests/test_cell.cc
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@ -36,7 +36,7 @@ static uint32_t xorshift32(uint32_t limit) {
return xorshift32_state % limit; return xorshift32_state % limit;
} }
static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode) static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
{ {
RTLIL::Module *module = design->addModule("\\gold"); RTLIL::Module *module = design->addModule("\\gold");
RTLIL::Cell *cell = module->addCell("\\UUT", cell_type); RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
@ -202,6 +202,13 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->setPort("\\Y", wire); cell->setPort("\\Y", wire);
} }
if (muxdiv && (cell_type == "$div" || cell_type == "$mod")) {
auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort("\\B"));
auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort("\\Y")));
module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort("\\Y"));
cell->setPort("\\Y", div_out);
}
if (cell_type == "$alu") if (cell_type == "$alu")
{ {
wire = module->addWire("\\CI"); wire = module->addWire("\\CI");
@ -529,6 +536,10 @@ struct TestCellPass : public Pass {
log(" -simlib\n"); log(" -simlib\n");
log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n"); log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
log("\n"); log("\n");
log(" -muxdiv\n");
log(" when creating test benches with dividers, create an additional mux\n");
log(" to mask out the division-by-zero case\n");
log("\n");
log(" -script {script_file}\n"); log(" -script {script_file}\n");
log(" instead of calling \"techmap\", call \"script {script_file}\".\n"); log(" instead of calling \"techmap\", call \"script {script_file}\".\n");
log("\n"); log("\n");
@ -552,6 +563,7 @@ struct TestCellPass : public Pass {
std::string ilang_file, write_prefix; std::string ilang_file, write_prefix;
xorshift32_state = 0; xorshift32_state = 0;
std::ofstream vlog_file; std::ofstream vlog_file;
bool muxdiv = false;
bool verbose = false; bool verbose = false;
bool constmode = false; bool constmode = false;
bool nosat = false; bool nosat = false;
@ -588,6 +600,10 @@ struct TestCellPass : public Pass {
techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc"; techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc";
continue; continue;
} }
if (args[argidx] == "-muxdiv") {
muxdiv = true;
continue;
}
if (args[argidx] == "-const") { if (args[argidx] == "-const") {
constmode = true; constmode = true;
continue; continue;
@ -729,7 +745,7 @@ struct TestCellPass : public Pass {
if (cell_type == "ilang") if (cell_type == "ilang")
Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file); Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file);
else else
create_gold_module(design, cell_type, cell_types.at(cell_type), constmode); create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
if (!write_prefix.empty()) { if (!write_prefix.empty()) {
Pass::call(design, stringf("write_ilang %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i)); Pass::call(design, stringf("write_ilang %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i));
} else { } else {