mirror of https://github.com/YosysHQ/yosys.git
scc to use design->selected_modules() which avoids black/white-boxes
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@ -301,41 +301,40 @@ struct SccPass : public Pass {
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RTLIL::Selection newSelection(false);
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int scc_counter = 0;
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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for (auto mod : design->selected_modules())
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{
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SccWorker worker(design, mod, nofeedbackMode, allCellTypes, maxDepth);
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if (!setAttr.empty())
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{
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SccWorker worker(design, mod_it.second, nofeedbackMode, allCellTypes, maxDepth);
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if (!setAttr.empty())
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for (const auto &cells : worker.sccList)
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{
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for (const auto &cells : worker.sccList)
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for (auto attr : setAttr)
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{
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for (auto attr : setAttr)
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{
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IdString attr_name(RTLIL::escape_id(attr.first));
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string attr_valstr = attr.second;
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string index = stringf("%d", scc_counter);
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IdString attr_name(RTLIL::escape_id(attr.first));
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string attr_valstr = attr.second;
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string index = stringf("%d", scc_counter);
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for (size_t pos = 0; (pos = attr_valstr.find("{}", pos)) != string::npos; pos += index.size())
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attr_valstr.replace(pos, 2, index);
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for (size_t pos = 0; (pos = attr_valstr.find("{}", pos)) != string::npos; pos += index.size())
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attr_valstr.replace(pos, 2, index);
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Const attr_value(attr_valstr);
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Const attr_value(attr_valstr);
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for (auto cell : cells)
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cell->attributes[attr_name] = attr_value;
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}
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scc_counter++;
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for (auto cell : cells)
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cell->attributes[attr_name] = attr_value;
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}
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}
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else
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{
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scc_counter += GetSize(worker.sccList);
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}
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if (selectMode)
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worker.select(newSelection);
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scc_counter++;
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}
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}
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else
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{
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scc_counter += GetSize(worker.sccList);
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}
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if (selectMode)
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worker.select(newSelection);
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}
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if (expect >= 0) {
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if (scc_counter == expect)
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