mirror of https://github.com/YosysHQ/yosys.git
scc to use design->selected_modules() which avoids black/white-boxes
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@ -301,10 +301,9 @@ struct SccPass : public Pass {
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RTLIL::Selection newSelection(false);
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int scc_counter = 0;
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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for (auto mod : design->selected_modules())
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{
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SccWorker worker(design, mod_it.second, nofeedbackMode, allCellTypes, maxDepth);
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SccWorker worker(design, mod, nofeedbackMode, allCellTypes, maxDepth);
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if (!setAttr.empty())
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{
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