From 86ab7d3a6ed994c06654fbae9770caa030f115d6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 12:07:08 -0700 Subject: [PATCH 1/7] kernel: Cell::getParam() to throw exception again if not found As it did before #1945 --- kernel/rtlil.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2aefe30b1..196e301b6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2619,16 +2619,15 @@ void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value) const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const { - static const RTLIL::Const empty; const auto &it = parameters.find(paramname); if (it != parameters.end()) return it->second; if (module && module->design) { RTLIL::Module *m = module->design->module(type); if (m) - return m->parameter_default_values.at(paramname, empty); + return m->parameter_default_values.at(paramname); } - return empty; + throw std::out_of_range("Cell::getParam()"); } void RTLIL::Cell::sort() From f582eb14af21450129e9cefbcaa5e7e3ad2e7783 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 13:57:09 -0700 Subject: [PATCH 2/7] xilinx: xilinx_dffopt to read cells_sim.v; fix test --- tests/arch/xilinx/xilinx_dffopt.ys | 35 +++++++++++++++++++----------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys index dc036acfd..2c729832e 100644 --- a/tests/arch/xilinx/xilinx_dffopt.ys +++ b/tests/arch/xilinx/xilinx_dffopt.ys @@ -18,17 +18,17 @@ FDRE ff (.D(tmp[0]), .CE(tmp[1]), .R(tmp[2]), .Q(o[0])); endmodule EOT - +read_verilog -lib +/xilinx/cells_sim.v design -save t0 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt design -load postopt clean +cd t0 select -assert-count 1 t:FDRE select -assert-count 1 t:LUT6 -select -assert-count 3 t:LUT2 -select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D +select -assert-none t:FDRE t:LUT6 %% t:* %D design -load t0 @@ -36,9 +36,10 @@ equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim design -load postopt clean +cd t0 select -assert-count 1 t:FDRE select -assert-count 1 t:LUT4 -select -assert-count 3 t:LUT2 +select -assert-count 1 t:LUT2 select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D design -reset @@ -65,16 +66,17 @@ endmodule EOT +read_verilog -lib +/xilinx/cells_sim.v design -save t0 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt design -load postopt clean +cd t0 select -assert-count 1 t:FDSE select -assert-count 1 t:LUT6 -select -assert-count 3 t:LUT2 -select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D +select -assert-none t:FDSE t:LUT6 %% t:* %D design -load t0 @@ -82,9 +84,10 @@ equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim design -load postopt clean +cd t0 select -assert-count 1 t:FDSE select -assert-count 1 t:LUT4 -select -assert-count 3 t:LUT2 +select -assert-count 1 t:LUT2 select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D design -reset @@ -111,15 +114,17 @@ endmodule EOT +read_verilog -lib +/xilinx/cells_sim.v design -save t0 equiv_opt -async2sync -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt design -load postopt clean +cd t0 select -assert-count 1 t:FDCE select -assert-count 1 t:LUT4 -select -assert-count 3 t:LUT2 +select -assert-count 1 t:LUT2 select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D design -reset @@ -145,16 +150,17 @@ endmodule EOT +read_verilog -lib +/xilinx/cells_sim.v design -save t0 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt design -load postopt clean +cd t0 select -assert-count 1 t:FDSE select -assert-count 1 t:LUT5 -select -assert-count 2 t:LUT2 -select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D +select -assert-none t:FDSE t:LUT5 %% t:* %D design -load t0 @@ -162,6 +168,7 @@ equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim design -load postopt clean +cd t0 select -assert-count 1 t:FDSE select -assert-count 2 t:LUT2 select -assert-none t:FDSE t:LUT2 %% t:* %D @@ -191,16 +198,17 @@ endmodule EOT +read_verilog -lib +/xilinx/cells_sim.v design -save t0 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt design -load postopt clean +cd t0 select -assert-count 1 t:FDRSE select -assert-count 1 t:LUT6 -select -assert-count 4 t:LUT2 -select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D +select -assert-none t:FDRSE t:LUT6 %% t:* %D design -load t0 @@ -208,9 +216,10 @@ equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim design -load postopt clean +cd t0 select -assert-count 1 t:FDRSE select -assert-count 1 t:LUT4 -select -assert-count 4 t:LUT2 +select -assert-count 1 t:LUT2 select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D design -reset From d2d90e4504a0fb43c35584484e0b949be7225b2b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 13:59:56 -0700 Subject: [PATCH 3/7] xilinx: improve xilinx_dffopt message --- techlibs/xilinx/xilinx_dffopt.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index c608db883..c9d63c9f7 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -292,18 +292,21 @@ unmap: LutData final_lut; if (worthy_post_r) { final_lut = lut_d_post_r; - log(" Merging R LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); } else if (worthy_post_s) { final_lut = lut_d_post_s; - log(" Merging S LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); } else if (worthy_post_ce) { final_lut = lut_d_post_ce; - log(" Merging CE LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); } else { // Nothing to do here. continue; } + std::string ports; + if (worthy_post_r) ports += " + R"; + if (worthy_post_s) ports += " + S"; + if (worthy_post_ce) ports += " + CE"; + log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + // Okay, we're doing it. Unmap ports. if (worthy_post_r) { cell->unsetParam(ID(IS_R_INVERTED)); From db09e96dff63b7b0fdb7010ad1965aaf261cbe2f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 16:35:35 -0700 Subject: [PATCH 4/7] test: ice40_dsp test to read +/ice40/cells_sim.v for default params --- tests/arch/ice40/ice40_dsp.ys | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys index 250273859..b13e525fd 100644 --- a/tests/arch/ice40/ice40_dsp.ys +++ b/tests/arch/ice40/ice40_dsp.ys @@ -8,4 +8,5 @@ assign o4 = a * b; SB_MAC16 m3 (.A(a), .B(b), .O(o5)); endmodule EOT +read_verilog -lib +/ice40/cells_sim.v ice40_dsp From 592baebd22ab1c80512b6f91926d90b33393285e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 17:43:25 -0700 Subject: [PATCH 5/7] xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only --- passes/pmgen/xilinx_dsp_cascade.pmg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index a36edd9e5..8babb88e6 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -188,7 +188,7 @@ arg next // driven by the 'P' output of the previous DSP cell, and (c) has its // 'PCIN' port unused match nextP - select !param(nextP, \CREG).as_bool() + select !nextP->type.in(\DSP48E1) || !param(nextP, \CREG).as_bool() select (nextP->type.in(\DSP48A, \DSP48A1) && port(nextP, \OPMODE, Const(0, 8)).extract(2,2) == Const::from_string("11")) || (nextP->type.in(\DSP48E1) && port(nextP, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")) select nusers(port(nextP, \C, SigSpec())) > 1 select nusers(port(nextP, \PCIN, SigSpec())) == 0 From 988d47af8533a0c7728095862dbc6a7311c1f8b7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 17:50:30 -0700 Subject: [PATCH 6/7] tests: read +/xilinx/cell_sim.v before xilinx_dsp test --- tests/arch/xilinx/xilinx_dsp.ys | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys index 3b9f52930..59d8296ab 100644 --- a/tests/arch/xilinx/xilinx_dsp.ys +++ b/tests/arch/xilinx/xilinx_dsp.ys @@ -8,4 +8,5 @@ assign o4 = a * b; DSP48E1 m3 (.A(a), .B(b), .P(o5)); endmodule EOT +read_verilog -lib +/xilinx/cells_sim.v xilinx_dsp From 51ae0f4e20815df98204b72bd740c00f5f2a1197 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Apr 2020 17:53:08 -0700 Subject: [PATCH 7/7] ecp5: ecp5_gsr to skip cells that don't have GSR parameter again --- techlibs/ecp5/ecp5_gsr.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc index 1c69e1d79..3d3f8e1c1 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/ecp5/ecp5_gsr.cc @@ -81,7 +81,7 @@ struct Ecp5GsrPass : public Pass { for (auto cell : module->selected_cells()) { - if (cell->getParam(ID(GSR)).decode_string() != "AUTO") + if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO") continue; bool gsren = found_gsr;