mirror of https://github.com/YosysHQ/yosys.git
break long chains
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@ -76,18 +76,15 @@ static void nx_carry_chain(Module *module)
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for(auto& c : carry_chains) {
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Cell *cell = nullptr;
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int j = 0;
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int cnt = 0;
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IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
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IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
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IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
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if (c.second.at(0)->getPort(ID(CI)).is_wire()) {
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SigBit new_co = module->addWire(NEW_ID);
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cell = module->addCell(NEW_ID, ID(NX_CY));
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cell->setPort(ID(CI), State::S0);
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cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
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cell->setPort(names_B[0], State::S0);
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cell->setPort(ID(CO), new_co);
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c.second.at(0)->setPort(ID(CI), new_co);
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j++;
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}
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@ -96,10 +93,24 @@ static void nx_carry_chain(Module *module)
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cell = module->addCell(NEW_ID, ID(NX_CY));
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cell->setPort(ID(CI), c.second.at(i)->getPort(ID(CI)));
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}
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if (j==3)
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cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO)));
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if (j==3) {
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cell->set_string_attribute(ID(cnt), std::to_string(cnt));
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if (cnt % 24 == 23) {
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SigBit new_co = module->addWire(NEW_ID);
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cell->setPort(ID(A4), State::S0);
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cell->setPort(ID(B4), State::S0);
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cell->setPort(ID(S4), new_co);
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cell = module->addCell(NEW_ID, ID(NX_CY));
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cell->setPort(ID(CI), State::S0);
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cell->setPort(ID(A1), new_co);
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cell->setPort(ID(B1), State::S0);
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j = 1;
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} else {
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if (c.second.at(i)->hasPort(ID(CO)))
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cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO)));
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}
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cnt++;
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}
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cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A))));
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cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B))));
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