mirror of https://github.com/YosysHQ/yosys.git
Added delete {-input|-output|-port}
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b3b5fac191
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@ -47,16 +47,34 @@ struct DeletePass : public Pass {
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log("Deletes the selected objects. This will also remove entire modules, if the\n");
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log("Deletes the selected objects. This will also remove entire modules, if the\n");
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log("whole module is selected.\n");
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log("whole module is selected.\n");
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log("\n");
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log("\n");
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log("\n");
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log(" delete {-input|-output|-port} [selection]\n");
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log("\n");
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log("Does not delete any object but removes the input and/or output flag on the\n");
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log("selected wires, thus 'deleting' module ports.\n");
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log("\n");
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}
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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{
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bool flag_input = false;
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bool flag_output = false;
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size_t argidx;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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{
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// if (arg[argidx] == "-something") {
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if (args[argidx] == "-input") {
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// flag_something = true;
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flag_input = true;
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// continue;
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continue;
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// }
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}
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if (args[argidx] == "-output") {
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flag_output = true;
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continue;
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}
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if (args[argidx] == "-port") {
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flag_input = true;
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flag_output = true;
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continue;
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}
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break;
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break;
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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@ -65,7 +83,7 @@ struct DeletePass : public Pass {
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for (auto &mod_it : design->modules)
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for (auto &mod_it : design->modules)
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{
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{
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if (design->selected_whole_module(mod_it.first)) {
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if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
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delete_mods.push_back(mod_it.first);
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delete_mods.push_back(mod_it.first);
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continue;
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continue;
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}
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}
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@ -74,6 +92,19 @@ struct DeletePass : public Pass {
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continue;
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continue;
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RTLIL::Module *module = mod_it.second;
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RTLIL::Module *module = mod_it.second;
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if (flag_input || flag_output) {
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for (auto &it : module->wires)
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if (design->selected(module, it.second)) {
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if (flag_input)
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it.second->port_input = false;
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if (flag_output)
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it.second->port_output = false;
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}
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module->fixup_ports();
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continue;
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}
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std::set<std::string> delete_wires;
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std::set<std::string> delete_wires;
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std::set<std::string> delete_cells;
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std::set<std::string> delete_cells;
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std::set<std::string> delete_procs;
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std::set<std::string> delete_procs;
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