mirror of https://github.com/YosysHQ/yosys.git
Add error for cell output ports that are connected to constants
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@ -620,34 +620,31 @@ struct HierarchyPass : public Pass {
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}
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}
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if (!keep_portwidths)
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for (auto module : design->modules())
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for (auto cell : module->cells())
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{
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for (auto module : design->modules())
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for (auto cell : module->cells())
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if (GetSize(cell->parameters) != 0)
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continue;
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Module *m = design->module(cell->type);
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if (m == nullptr || m->get_bool_attribute("\\blackbox"))
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continue;
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for (auto &conn : cell->connections())
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{
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if (GetSize(cell->parameters) != 0)
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Wire *w = m->wire(conn.first);
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if (w == nullptr || w->port_id == 0)
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continue;
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Module *m = design->module(cell->type);
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if (m == nullptr || m->get_bool_attribute("\\blackbox"))
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if (GetSize(conn.second) == 0)
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continue;
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for (auto &conn : cell->connections())
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SigSpec sig = conn.second;
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if (!keep_portwidths && GetSize(w) != GetSize(conn.second))
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{
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Wire *w = m->wire(conn.first);
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if (w == nullptr || w->port_id == 0)
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continue;
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if (GetSize(conn.second) == 0)
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continue;
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if (GetSize(w) == GetSize(conn.second))
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continue;
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SigSpec sig = conn.second;
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if (GetSize(w) < GetSize(conn.second))
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{
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int n = GetSize(conn.second) - GetSize(w);
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@ -669,6 +666,10 @@ struct HierarchyPass : public Pass {
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log_id(conn.first), GetSize(conn.second), GetSize(sig));
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cell->setPort(conn.first, sig);
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}
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if (w->port_output && !w->port_input && sig.has_const())
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log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
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log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
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}
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}
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